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Multiplexed, Multi-Electrode Neurostimulation Devices with Integrated Circuits Having Integrated Electrodes

Application Number: 20120035684
Publication Date: 2012-02-09
Inventors: Jensen, Marc; Strand, Angela; Thompson, Todd; Zdeblick, Mark

Implantable stimulation devices are provided. Aspects of the devices include a multiplexed multi-electrode component configured for neural stimulation. The multiplexed multi-electrode component includes two or more individually addressable satellite electrode structures electrically coupled to a common conductor. The satellite structures include a hermetically sealed integrated control circuit operatively coupled to one or more electrodes. Also provided are methods of manufacturing wherein the ...

Volatile Imidazoles and Group 2 Imidazole Based Metal Precursors

Application Number: 20120035351
Publication Date: 2012-02-09
Inventors: Kim, Moo-Sung; Norman, John Anthony Thomas; Perez, Melanie K.

Sterically hindered imidazole ligands are described, along with their synthesis, which are capable of coordinating to Group 2 metals, such as: calcium, magnesium, strontium, in an eta-5 coordination mode which permits the formation of monomeric or dimeric volatile complexes.

A compound comprising one or more polysubstituted imidazolate anions coordinated to a metal selected from the group consisting of barium, strontium, magnesium, radium or calcium or mixtures ...

ENHANCING THE WIDTH OF POLYCRYSTALLINE GRAINS WITH MASK

Application Number: 20120034794
Publication Date: 2012-02-09
Inventor: Im, James S.

A system, method and masking arrangement are provided of enhancing the width of polycrystalline grains produced using sequential lateral solidification using a modified mask pattern is disclosed. One exemplary mask pattern employs rows of diamond or circular shaped areas in order to control the width of the grain perpendicular to the direction of primary ...

METHOD FOR FORMING METAL NITRIDE FILM

Application Number: 20120034793
Publication Date: 2012-02-09
Inventors: Kakimoto, Akinobu; Narushima, Kensaku; Hotta, Takanobu

A wafer serving as a target substrate to be processed is loaded into a chamber, and an inside of the chamber is maintained under a vacuum level. Then, a TiN film is formed on the wafer by alternately supplying TiCl₄gas and MMH gas into the chamber while heating the wafer. NH₃gas is supplied in conjunction with the supply of the hydrazine compound ...

COATING TREATMENT METHOD

Application Number: 20120034792
Publication Date: 2012-02-09
Inventors: YOSHIHARA, Kousuke; Iseki, Tomohiro

The present invention supplies a solvent to a front surface of a substrate while rotating the substrate. The substrate is acceleratingly rotated to a first number of rotations, and a resist solution is supplied to a central portion of the substrate during the accelerating rotation and the rotation at a first number of rotations. The substrate is deceleratingly rotated to a second number of rotations, and after the number of rotations of the substrate reaches the second number of rotations, the ...

METHOD OF FLATTENING A RECESS IN A SUBSTRATE AND FABRICATING A SEMICONDUCTOR STRUCTURE

Application Number: 20120034791
Publication Date: 2012-02-09
Inventors: Lay, Chao-Wen; Lin, Ching-Kai

A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed ...

METHOD OF PRODUCING SEMICONDUCTOR DEVICE

Application Number: 20120034790
Publication Date: 2012-02-09
Inventors: Toyoda, Kazuyuki; Mizuno, Norikazu; Miya, Hironobu; Asai, Masayuki; Sato, Taketoshi; Horita, Hideki; Okuda, Kazuyuki; Sakai, Masanori

Disclosed is a producing method of a semiconductor device comprising a first step of supplying a first reactant to a substrate to cause a ligand-exchange reaction between a ligand of the first reactant and a ligand as a reactive site existing on a surface of the substrate, a second step of removing a surplus of the first reactant, a third step of supplying a second reactant to the substrate to cause a ligand-exchange reaction to change the ligand after the exchange in the first step into a ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Application Number: 20120034789
Publication Date: 2012-02-09
Inventors: Matsunaga, Kentaro; Ito, Shinichi

A method for manufacturing a semiconductor device includes: performing modifying a surface of a semiconductor wafer including a silanol group on the surface with an alkylsilyl group; and fluorinating an alkyl group of the alkylsilyl group with which the surface was ...

SUBSTRATE PROCESSING APPARATUS AND PRODUCING METHOD OF SEMICONDUCTOR DEVICE

Application Number: 20120034788
Publication Date: 2012-02-09
Inventors: Kagaya, Toru; Yamazaki, Hirohisa; Sakai, Masanori

A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O₃) are alternately fed into the reaction tubeto generate Al₂O₃film on the surface of the wafer. The apparatus also includes supply tubes and for flowing the ozone and TMA and a nozzle supplying gas into the reaction tube. The two supply tubes are connected to the nozzle disposed inside the heater in a zone inside the reaction tube ...

Defect Etching of Germanium

Application Number: 20120034787
Publication Date: 2012-02-09
Inventors: Souriau, Laurent; Terzieva, Valentina

The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min⁻¹and 450 nm·min⁻¹, which makes it suitable to be used for revealing defects in a thin layer of germanium, i.e. in a ...

Plasma Processing Chamber with Dual Axial Gas Injection and Exhaust

Application Number: 20120034786
Publication Date: 2012-02-09
Inventors: Bailey, III, Andrew D.; Dhindsa, Rajinder; Marakhatnov, Alexei

An electrode is exposed to a plasma generation volume and is defined to transmit radiofrequency power to the plasma generation volume, and includes an upper surface for holding a substrate in exposure to the plasma generation volume. A gas distribution unit is disposed above the plasma generation volume and in a substantially parallel orientation to the electrode. The gas distribution unit includes an arrangement of gas supply ports for directing an input flow of a plasma process gas into the ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Application Number: 20120034785
Publication Date: 2012-02-09
Inventors: HAYASHI, Hisataka; Kasahara, Yusuke; Imamura, Tsubasa

According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not ...

Methods of Forming Fine Patterns in Semiconductor Devices

Application Number: 20120034784
Publication Date: 2012-02-09
Inventors: Kim, Bum-Soo; Min, Jae-Ho; Kim, Dong-chan; Kim, Myeong-cheol; Kwon, O-lk

Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and ...

MANUFACTURING INTEGRATED CIRCUIT COMPONENTS HAVING MULTIPLE GATE OXIDATIONS

Application Number: 20120034783
Publication Date: 2012-02-09
Inventors: Entalai, Wilson; Liew, Jerry

STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (150) having a thickness less than 150 then a oxide cover layer (160) having a thickness less than 150 is deposited acting as implant buffer after pad oxide removal following the STI CMP process. This nitride or oxide stack is selectively removed by masking prior to gate oxidation of each LV (low voltage) region (GX1), MV (intermediate voltage) ...

Method of Forming Fine Patterns

Application Number: 20120034782
Publication Date: 2012-02-09
Inventor: Kim, Choong Bae

A method of forming fine patterns according to an aspect of the present disclosure comprises stacking a hard mask layer and a first auxiliary layer over an underlying layer, removing regions of the first auxiliary layer, thereby forming first auxiliary patterns to expose regions of the hard mask layer, filling between the first auxiliary patterns with a second auxiliary layer, wherein a material of the second auxiliary layer is different from that of the first auxiliary layer, lowering a height ...

METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE

Application Number: 20120034781
Publication Date: 2012-02-09
Inventor: Kuo, Lung-En

A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material ...

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

Application Number: 20120034780
Publication Date: 2012-02-09
Inventors: Chen, Shin-Chi; Chen, Chieh-Te; Shih, Hung-Ling; Huang, Wei-Hang

A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and ...

APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Application Number: 20120034779
Publication Date: 2012-02-09
Inventors: Asako, Ryuichi; Kubota, Kazuhiro; SHIMURA, Satoru; Takayama, Seiichi

In a semiconductor device manufacturing method, an etching mask (75b) having a predetermined opening pattern is formed on an etching target film (74) disposed on a target object. Then, an etching process is performed on the etching target film (74) through the opening pattern of the etching mask (75b) within a first process chamber, thereby forming a groove or hole (78a) in the etching target film. Then, the target object treated by the ...

Double Patterning Strategy for Contact Hole and Trench in Photolithography

Application Number: 20120034778
Publication Date: 2012-02-09
Inventors: Chen, Jian-Hong; Hsu, Feng-Cheng

A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including a plurality of openings therein on the substrate; forming a second resist pattern on the substrate and within the plurality of openings of the first resist pattern, the second resist pattern including at least one opening therein on the substrate; and removing the first resist pattern to uncover the substrate underlying the first resist ...

Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection

Application Number: 20120034777
Publication Date: 2012-02-09
Inventors: Pagaila, Reza A.; Do, Byung Tai; Camacho, Zigmund R.; Tay, Lionel Chien Hui

A semiconductor package includes a semiconductor wafer having a plurality of semiconductor die. A contact pad is formed over and electrically connected to an active surface of the semiconductor die. A gap is formed between the semiconductor die. An insulating material is deposited in the gap between the semiconductor die. An adhesive layer is formed over a surface of the semiconductor die and the insulating material. A via is formed in the insulating material and the adhesive layer. A ...

DEVICE OF FILLING METAL IN THROUGH-VIA-HOLE OF SEMICONDUCTOR WAFER AND METHOD USING THE SAME

Application Number: 20120034776
Publication Date: 2012-02-09
Inventors: Kim, Jeong Han; Yoo, Se Hoon; Lee, Chang Woo; Kim, Jun Ki; Kim, Cheol Hee; Ko, Young Ki; Shin, Yue Seon

A device of filling metal in a through-via-hole formed in a semiconductor wafer and a method of filling metal in a through-via-hole using the same are disclosed. A device of filling metal in a through-via-hole formed in a semiconductor wafer includes a jig base comprising a jig configured to fix the wafer having the through-via-hole formed therein; a upper chamber 120 installed on the jig base; a lower chamber installed under the jig base; a heater installed in the upper chamber, the heater ...

Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

Application Number: 20120034775
Publication Date: 2012-02-09
Inventor: Lee, Il Kwan

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; ...

Energy Conditioning Circuit Arrangement for Integrated Circuit

Application Number: 20120034774
Publication Date: 2012-02-09
Inventors: Anthony, Anthony A.; Anthony, William M.

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The ...

TRANSISTOR HAVING AN ETCH STOP LAYER INCLUDING A METAL COMPOUND THAT IS SELECTIVELY FORMED OVER A METAL GATE, AND METHOD THEREFOR

Application Number: 20120034773
Publication Date: 2012-02-09
Inventors: Ott, Andrew; Sharma, Ajay; King, Sean

In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also ...

Nonvolatile Semiconductor Memory Device Having Multi-Layered Oxide/(OXY) Nitride Film as Inter-Electrode Insulating Film and Manufacturing Method Thereof

Application Number: 20120034772
Publication Date: 2012-02-09
Inventors: TANAKA, Masayuki; OZAWA, Yoshio; ISHIDA, Hirokazu

A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof ...

BOND PAD FOR LOW K DIELECTRIC MATERIALS AND METHOD FOR MANUFACTURE FOR SEMICONDUCTOR DEVICES

Application Number: 20120034771
Publication Date: 2012-02-09
Inventor: NING, XIAN J.

A method for manufacturing a semiconductor device having improved contact structure includes providing a semiconductor substrate, forming a plurality of gate structures formed on a portion of the substrate, forming an interlayer dielectric layer overlying the gate structures, and forming a first copper interconnect layer overlying the substantially flat surface region of the interlayer dielectric layer. The method further includes forming a dielectric layer overlying the first copper ...

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

Application Number: 20120034770
Publication Date: 2012-02-09
Inventors: Hwang, Yong-Sup; Chae, Gee-Sung

A liquid crystal display device includes a plurality of gate lines and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistors, each disposed in one of the pixel regions, and a plurality of pixel electrodes, each disposed in one of the pixel regions, wherein the thin film transistor includes at least one Ti ...

LOW TEMPERATURE MICROWAVE ACTIVATION OF HEAVY BODY IMPLANTS

Application Number: 20120034769
Publication Date: 2012-02-09
Inventors: Purtell, Robert J.; Dunn, Dixie

Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dopant regions that have been formed by low temperature, microwave activation of implanted dopants. In some configurations, the low temperature microwave activation can be used to control the final location of the implant, with or without additional drive-in or implant processes. In some configurations, this control can be used to create heavy body implants. Microwave activation of source ...

METHOD OF MANUFACTURING SEMICONDUCTOR WAFER

Application Number: 20120034768
Publication Date: 2012-02-09
Inventor: SATO, Ken

A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the ...

Method of Making a Multicomponent Film

Application Number: 20120034767
Publication Date: 2012-02-09
Inventors: Buchanan, Iain; Xiao, Manchao; Lei, Xinjian; Yang, Liu

Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium ...

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Application Number: 20120034766
Publication Date: 2012-02-09
Inventors: MIYANAGA, Akiharu; ZHANG, Hongyong; OHTANI, Hisashi; FUKUNAGA, Takeshi

A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the ...

MANUFACTURING METHOD OF MICROCRYSTALLINE SILICON FILM AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR

Application Number: 20120034765
Publication Date: 2012-02-09
Inventors: MIYAIRI, Hidekazu; IENAGA, Takashi; MORIGUCHI, Masao; KANZAKI, Yosuke

An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a ...

SYSTEM AND METHOD FOR FABRICATING THIN-FILM PHOTOVOLTAIC DEVICES

Application Number: 20120034764
Publication Date: 2012-02-09
Inventors: Sferlazzo, Piero; Lampros, Thomas Michael

Described are an apparatus and a method for depositing a thin film on a web. The method includes depositing a first layer of a composite metal onto a web. A first selenium layer is deposited onto the first layer and the web is heated to selenize the first layer. Subsequently, a second layer of the composite metal is deposited onto the selenized first layer and a second selenium layer is deposited onto the second layer. The web is then heated to selenize the second layer. The composition of each ...

Method of Manufacturing Nitride Semiconductor Substrate

Application Number: 20120034763
Publication Date: 2012-02-09
Inventors: Nakanishi, Fumitake; Uematsu, Koji; Osada, Hideki; Nakahata, Seiji

The present invention provides a method of manufacturing a nitride semiconductor substrate capable of efficiently manufacturing a nitride semiconductor substrate having a nonpolar plane as a major surface in which polycrystalline growth is minimized. A method of manufacturing a GaN substrate, which is a nitride semiconductor substrate, includes steps (S10 and S20) of preparing a starting substrate composed of GaN and having a major surface with an off-axis angle of between 4.1° ...

Method for Selective Deposition of a Semiconductor Material

Application Number: 20120034762
Publication Date: 2012-02-09
Inventors: Verheyen, Peter; Severi, Simone; Bryce, George

A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is ...

METHOD OF REMOVING CONTAMINANTS AND NATIVE OXIDES FROM A SUBSTRATE SURFACE

Application Number: 20120034761
Publication Date: 2012-02-09
Inventors: Hemkar, Manish; Kuppurao, Satheesh; Tran, Vinh; Kim, Yihwan

Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include exposing a substrate having an oxide layer thereon to an oxidizing source. The oxidizing source oxidizes an upper portion of the substrate beneath the oxide layer to form an oxide layer having an increased thickness. The oxide layer with the increased thickness is then removed to expose a clean surface of the substrate. The removal ...

Metallization for Chip Scale Packages in Wafer Level Packaging

Application Number: 20120034760
Publication Date: 2012-02-09
Inventors: Ahrens, Carsten; Schuderer, Berthold

In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Application Number: 20120034759
Publication Date: 2012-02-09
Inventors: Yonehara, Takao; Kawase, Nobuo; Sakaguchi, Kiyofumi; Nakagawa, Kenji

A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor ...

METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE

Application Number: 20120034758
Publication Date: 2012-02-09
Inventor: KOEZUKA, Junichi

A cap film which can prevent diffusion of hydrogen from the embrittled region and supply hydrogen to a region between the embrittled region and the surface of the semiconductor substrate is formed over the semiconductor substrate, and the semiconductor layer is transferred from the semiconductor substrate to the base substrate. In particular, the amount of hydrogen contained in the cap film formed over the semiconductor substrate is preferably greater than or equal to the irradiation amount of ...

METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING VARIOUS ISOLATION REGIONS

Application Number: 20120034757
Publication Date: 2012-02-09
Inventors: Choi, Yong-Soon; Kim, Hong-Gun; Hong, Eunkee; Choi, Gil-Heyun; Yi, Ha-Young; Lee, Jun-Won

A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second ...

Method of Forming a Deep Trench Isolation Structure Using a Planarized Hard Mask

Application Number: 20120034756
Publication Date: 2012-02-09
Inventors: Kwon, Taehun; Hill, Rodney L.; Sehgal, Akshey; Getchell, Donald Robertson; McCarthy, Patrick; Leng, Yaojian

A number of deep trench openings are formed in a semiconductor wafer to have substantially equal depths and no oxide undercut by forming a number of shallow trench openings, forming a mask structure in the shallow trench openings where the mask structure has a substantially planar top surface, forming a number of mask openings in the mask structure, and etching the semiconductor wafer through the mask openings to form the deep trench ...

METHOD AND MANUFACTURE FOR HIGH VOLTAGE GATE OXIDE FORMATION AFTER SHALLOW TRENCH ISOLATION FORMATION

Application Number: 20120034755
Publication Date: 2012-02-09
Inventors: Wang, Fei; Lin, Chih-Yun

A method and manufacture for fabrication of flash memory is provided. In fabricating the periphery region of the flash memory, the low voltage gate oxides and high voltage gate oxides are grown to the same height as each other prior to STI etching. After STI etching and gap fill, the nitride above the high voltage gate oxide regions are etched, and the oxide in high voltage gate oxide regions is grown to the appropriate thickness for a high voltage gate ...

SEMICONDUCTOR DEVICE MANUFACATURING METHOD AND SILICON OXIDE FILM FORMING METHOD

Application Number: 20120034754
Publication Date: 2012-02-09
Inventors: Nakazawa, Keisuke; Sekine, Katsuyuki; Matsuo, Shogo; Hoshi, Takeshi; Kato, Ryu; Iwasawa, Kazuaki; Nakao, Takashi; Kai, Tetsuya

A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a ...

Methods of Forming a Plurality of Capacitors

Application Number: 20120034753
Publication Date: 2012-02-09
Inventors: Bhat, Vishwanath; Shea, Kevin R.

A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. ...

METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME

Application Number: 20120034752
Publication Date: 2012-02-09
Inventors: KIM, Weon-Hong; Jung, Hyung-Suk; Lim, Ha-Jin

In a method of forming a gate structure, a gate pattern including a gate insulation layer pattern and a gate electrode sequentially stacked on a substrate is formed. The gate electrode includes a metal. A first plasma process is performed on the gate pattern using a reaction gas to reduce an oxidized edge portion of the gate electrode. The reaction gas includes nitrogen. A spacer is formed on a sidewall of the gate pattern. A threshold voltage is adjusted by reducing the oxidized edge portion ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Application Number: 20120034751
Publication Date: 2012-02-09
Inventors: Ariyoshi, Junichi; Ema, Taiji; Anezaki, Toru

A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND PLASMA DOPING APPARATUS

Application Number: 20120034750
Publication Date: 2012-02-09
Inventors: Kubota, Masafumi; Hayashi, Shigenori; Sasaki, Yuichiro

After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region ...

METHOD FOR MANUFACTURING A STRAINED SEMICONDUCTOR DEVICE

Application Number: 20120034749
Publication Date: 2012-02-09
Inventors: Lee, Hyun-Jung; Koh, Chung-Geun; LIM, Kwan-Yong; Kwon, Tae-Ouk; Kim, Seok-Hoon; Cha, Tae-Ho

A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the ...

METHOD OF FABRICATING TRANSISTOR FOR SEMICONDUCTOR DEVICE

Application Number: 20120034748
Publication Date: 2012-02-09
Inventor: SHIN, Min-Jung

A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Application Number: 20120034747
Publication Date: 2012-02-09
Inventor: Lin, Chun-Hsien

A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between ...