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		    <title>PatentStorm ->  Applications -> Amplifiers</title>
		    <link>http://www.patentstorm.us/rss/class/applications/rss-330.xml</link>
		    <description>Recent patent applications filings in USPTO Class 330 Amplifiers.</description>
		    <pubDate>Thu, 9 Feb 2012 15:03:27</pubDate>
		    <managingEditor>patents@patentstorm.us</managingEditor>
		    <language>en</language><item>
			         <title><![CDATA[SYSTEM AND METHOD FOR BIASING A POWER AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120034956/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120034956</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Sawatzky, David; Green, Duane A.; Shu, Weiwei</li></ul>A system and method for biasing a power amplifier includes a power amplifier having a driver stage and an output stage, the driver stage having a plurality of driver devices, a bias current source configured to deliver a bias current to each of the plurality of driver devices, and a current directing element configured to receive the bias current and selectively bias each of the plurality of driver devices based on a reference voltage and a system ...<br />]]></description>		         
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			         <title><![CDATA[OPERATIONAL AMPLIFIER CIRCUIT, SIGNAL DRIVER, DISPLAY DEVICE, AND OFFSET VOLTAGE ADJUSTING METHOD]]></title>
			         <link>http://www.patentstorm.us/applications/20120032944/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032944</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;KOJIMA, Tomokazu</li></ul>Provided is an operational amplifier circuit including a Rail-to-Rail differential amplifier including: first and second differential transistors forming a first differential pair; and third and fourth differential transistors forming a second differential pair, wherein each of the first and second differential transistors is an n-type MOS transistor, each of the third and fourth differential transistors is a p-type MOS transistor, and the operational amplifier circuit further includes: a first ...<br />]]></description>		         
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			         <title><![CDATA[SIGNAL DRIVER AND DISPLAY DEVICE]]></title>
			         <link>http://www.patentstorm.us/applications/20120032932/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032932</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;KOJIMA, Tomokazu</li></ul>Provided is a signal driver including: operational amplifier circuits; a voltage generating unit configured to generate voltage signals; and selecting units configured to select one of the voltage signals, and to output the selected voltage signal as a correction voltage signal to a corresponding one of the operational amplifier circuits, each of the operational amplifier circuits including a differential amplifier and a correction current supply unit, and the differential amplifier including: ...<br />]]></description>		         
			         <guid isPermaLink="false">20120032932</guid>
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			         <title><![CDATA[ADDER-EMBEDDED DYNAMIC PREAMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032831/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032831</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Temes, Gábor C.; Chae, Jeongseok</li></ul>A method and apparatus for an adder-embedded dynamic preamplifier system with dynamic comparator and current mode adder including differential switches for precharging, a switch for evaluation; and reference, feedfoward input sections. When differential switches are closed, OUTN and OUTP are precharged. During the evaluation, discharging currents are proportionately determined by input and reference values. A following latch amplifies the discharging differences of OUTN and ...<br />]]></description>		         
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			         <title><![CDATA[POWER AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032744/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032744</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Maki, Suguru</li></ul>A power amplifier comprises: an amplifier transistor; a bias circuit supplying bias current to the amplifier transistor; and a collector voltage terminal connected to a collector of the amplifier transistor. The bias circuit includes: a reference voltage terminal into which a reference voltage is input; a power terminal connected to a power source; a transistor having a control terminal connected to the reference voltage terminal, a first terminal connected to the power terminal, and a second ...<br />]]></description>		         
			         <guid isPermaLink="false">20120032744</guid>
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			         <title><![CDATA[LOW-NOISE AMPLIFIER WITH GAIN ENHANCEMENT]]></title>
			         <link>http://www.patentstorm.us/applications/20120032743/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032743</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;HSUEH, Fu-Lung; JOU, Chewn-Pu; HSIEH, Hsieh-Hung; WU, Po-Yi; CHEN, Ho-Hsiang</li></ul>A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes ...<br />]]></description>		         
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			         <title><![CDATA[CMOS MILLIMETER-WAVE VARIABLE-GAIN LOW-NOISE AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032742/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032742</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;HSUEH, Fu-Lung; JOU, Chewn-Pu; HSIEH, Hsieh-Hung; WU, Po-Yi; CHEN, Ho-Hsiang</li></ul>A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to ...<br />]]></description>		         
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			         <title><![CDATA[Integrated Bluetooth and Wireless LAN Transceivers Having Merged Low Noise and Power Amplifier]]></title>
			         <link>http://www.patentstorm.us/applications/20120032741/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032741</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;DE MAAIJER, Luc</li></ul>A group of transistors operate as a combined power amplifier, to amplify signals to be transmitted, and as a low noise amplifier, to amplify signals which are received. In a first mode, the group of transistors is configured to amplify the signals to be transmitted by turning all of the transistors in both a first subset and a second subset on. In a second mode, the group of transistors is configured to amplify the signals which have been received by turning on the first subset of transistors ...<br />]]></description>		         
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			         <title><![CDATA[AMPLIFIER FOR RECEIVING INTERMITTENT OPTICAL SIGNAL]]></title>
			         <link>http://www.patentstorm.us/applications/20120032740/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032740</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Sawada, Sosaku; Hara, Hiroshi</li></ul>An amplifier for receiving an optical signal is disclosed. The amplifier provides a response time controller including an integrator with two time constants, a linear amplifier, a hysteresis comparator, an another integrator, and a switch to change the time constant. The switch includes two voltage followers, one of which turns off the switch to set the time constant in a longer state; while, the other of which turns on the switch and reflects the input of the integrator to set the time ...<br />]]></description>		         
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			         <title><![CDATA[DIGITAL PREDISTORTION CIRCUIT WITH EXTENDED OPERATING RANGE AND A METHOD THEREOF]]></title>
			         <link>http://www.patentstorm.us/applications/20120032739/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032739</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Peroulas, James; Dai, Zhengjian</li></ul>A digital predistortion circuit and method with extended operating range includes a predistortion function, a D/A converter, a multiplier for performing frequency translation and a power amplifier. The digital predistortion circuit includes a multiplier for receiving a signal to be transmitted and a gain correction factor, multiplying the gain correction factor with the signal to be transmitted, and outputting a result of the multiplication to the predistortion function, as well as a device for ...<br />]]></description>		         
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			         <title><![CDATA[POWER AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032738/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032738</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Uchiyama, Kazuhiro</li></ul>An efficient power amplifier with a design which, even in cases when the phase characteristics of high frequency devices used in a main amp and peaking amp differ, reduces the combination loss of the two amps at a wide range of output levels. A class AB power amplifier (<b>103</b>) using an LDMOS device amplifies divided input signals, and a class AB power amplifier (<b>104</b>) using a GaN device amplifies the signals output from the power amplifier (<b>103</b>). Further, a class C power ...<br />]]></description>		         
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			         <title><![CDATA[ON-CHIP MILLIMETER WAVE LANGE COUPLER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032737/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032737</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Lam, Kwan Him; Ding, Hanyi</li></ul>A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are ...<br />]]></description>		         
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			         <title><![CDATA[AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120027127/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120027127</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;KATO, Takayuki</li></ul>An amplifier includes a separating unit, a generator, first to fourth switching amplifiers, and an outputting unit. The separating unit separates a pulse signal into a first separated pulse signal and a second separated pulse signal. The generator generates first to fourth low speed pulse signals by using the first and the second separated pulse signal. The first switching amplifier amplifies the first low speed pulse signal. The second switching amplifier amplifies the second low speed pulse ...<br />]]></description>		         
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			         <title><![CDATA[Efficient amplification stage]]></title>
			         <link>http://www.patentstorm.us/applications/20120025917/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025917</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Wimpenny, Gerard; Flint, Shane</li></ul>This is disclosed an amplification stage including a first amplifier stage, a second amplifier stage, and a power supply unit, in which the output of the first stage provides the input to the second stage, and the power supply unit provides a power supply for both amplifier stages, wherein the voltage of the power supply is continuously varied in dependence of the amplitude of the signal being ...<br />]]></description>		         
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			         <title><![CDATA[DOHERTY AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120025916/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025916</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;Deguchi, Hiroaki</li></ul>An amplifier includes a Doherty amplifier composed of a distributor distributing an input signal to two signals, a carrier amplifier that receives one of the two signals and has a first FET, a peaking amplifier that receives the other one of the two signals and has a second FET, and a combiner that transforms an output impedance of the carrier amplifier and combines outputs of the carrier amplifier and the peaking amplifier, and a voltage controller that changes at least one of a gate voltage ...<br />]]></description>		         
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			         <title><![CDATA[DOHERTY AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120025915/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025915</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;Ui, Norihiko</li></ul>A Doherty amplifier includes: an input distributor; a coupler; a plurality of Doherty circuit connected between the input distributor and the coupler; wherein each of Doherty circuits has a carrier amplifier, a peaking amplifier, a distributor distributing a input signal to the carrier amplifier and the peaking amplifier, and a combiner that transforms an output impedance of the carrier amplifier and combines outputs of the carrier amplifier and the peaking ...<br />]]></description>		         
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			         <title><![CDATA[CMOS POWER AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120025914/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025914</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;KIM, Ki Joong; NAM, Joong Jin; WON, Jun Goo; KIM, Youn Suk; YOON, Chul Hwan</li></ul>A CMOS power amplifier includes: a first MOS transistor connected between a first power terminal and a first output stage and having a gate connected to an input stage; a second MOS transistor connected between the first output stage and a ground and having a gate connected to the input stage; a switching circuit unit connecting or separating a feedback line between the input stage and the first output stage to select a linear amplifying operation or a non-linear amplifying operation; and a ...<br />]]></description>		         
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			         <title><![CDATA[Envelope amplifier]]></title>
			         <link>http://www.patentstorm.us/applications/20120025913/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025913</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Honda, Yuri; Takahashi, Yuji</li></ul>An envelope amplifier includes an amplifier unit, a comparator unit and an output unit. The amplifier unit is made up of a first output section that outputs a first current in response to an amplitude of an input envelope signal, and a second output section. The second output section outputs a second current of a current value proportionate to a current value of the first current. Absolute value of the current value of the second current is greater than that of a current value of the first ...<br />]]></description>		         
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			         <title><![CDATA[DIFFERENTIAL AMPLIFIER CIRCUIT]]></title>
			         <link>http://www.patentstorm.us/applications/20120025912/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025912</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;OOMORI, Tetsuo</li></ul>A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal ...<br />]]></description>		         
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			         <title><![CDATA[Low Noise Amplifier with Current Bleeding Branch]]></title>
			         <link>http://www.patentstorm.us/applications/20120025911/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025911</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Zhao, Zhongwu; Jin, Xiaodong</li></ul>An LNA circuit for providing a wide range of gain while maintaining the output headroom. In a radio frequency (RF) receiver, the signal received by the receiver may be extremely small. For a transmitter in a short distance, the received signal may be relatively strong. A low power amplifier usually is used to amplify the input signal. The LNA has to be designed to accommodate a wide range of gain. A convention LNA circuit supporting a wide range of gain often suffers from reduced output ...<br />]]></description>		         
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			         <title><![CDATA[Switching amplifier with enhanced supply rejection and related method]]></title>
			         <link>http://www.patentstorm.us/applications/20120025910/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025910</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Jiang, Xicheng; Brooks, Todd L.; Song, Jungwoo; Wang, Minsheng</li></ul>Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby ...<br />]]></description>		         
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			         <title><![CDATA[DISTORTION COMPENSATION APPARATUS AND APPARATUS AND METHOD FOR TRANSMITTING SIGNAL]]></title>
			         <link>http://www.patentstorm.us/applications/20120025909/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025909</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Chung, Hyun-Kyu; Jo, Gweon-Do; Oh, Jung-Hoon; Kim, Joon-Hyung; Kim, Young-Hoon; Jung, Jae-Ho</li></ul>A distortion compensation apparatus and an apparatus and method for transmitting a signal are provided. The distortion compensation apparatus can extract precise distortion information by adding an additional signal to an input signal during the compensation of distortion in a nonlinear apparatus, and can linearize the nonlinear properties of the nonlinear apparatus using the distortion information. The apparatus for transmitting a signal can output a signal linearized by the same method as ...<br />]]></description>		         
			         <guid isPermaLink="false">20120025909</guid>
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			         <title><![CDATA[AUTOMATIC GAIN CONTROL]]></title>
			         <link>http://www.patentstorm.us/applications/20120025908/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025908</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;Reining, Friedrich</li></ul>An automatic gain controller is disclosed. The AGC includes an input for monitoring a signal associated with an amplifier and a gain control circuit for controlling the gain of the amplifier in response to the monitored signal, wherein the gain control circuit is adapted to control the gain of the amplifier in accordance with a gain control function having continuously variable attack and release time constants, both of which depend on the amplitude of the monitored ...<br />]]></description>		         
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			         <title><![CDATA[POWER AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120025907/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025907</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Na, Yoo Sam; KIM, Gyu Suck; KOO, Bon Hoon; SON, Ki Yong; HONG, Song Cheol</li></ul>There is provided a power amplifier capable of supplying variable bias to an amplifier circuit by accurately transferring the envelope components of an input signal during the supply of active bias power to the amplifier circuit. The power amplifier includes: an envelope detector detecting an envelope of an input signal; a bias power generator including at least one P-type MOSFET and one N-type MOSFET connected to each other in an inverter manner between a driving power terminal supplying ...<br />]]></description>		         
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			         <title><![CDATA[Systems and Methods of RF Power Transmission, Modulation, and Amplification, Including Embodiments for Compensating for Waveform Distortion]]></title>
			         <link>http://www.patentstorm.us/applications/20120025906/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120025906</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Rawlins, Gregory S.; Rawlins, Michael W.; SORRELLS, David F.</li></ul>Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is ...<br />]]></description>		         
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			         <title><![CDATA[Concurrent impedance and noise matching transconductance amplifier and receiver implementing same]]></title>
			         <link>http://www.patentstorm.us/applications/20120021713/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120021713</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Mikhemar, Mohyee; Darabi, Hooman</li></ul>According to one embodiment, a concurrent impedance and noise matching transconductance amplifier designed for implementation in a receiver comprises an input device configured to couple to a matching network of the receiver, and a boost capacitor connected to the input device to increase an input capacitance of the transconductance amplifier. The boost capacitor is selected to substantially minimize the receiver noise and to enable the concurrent impedance and noise matching of the receiver ...<br />]]></description>		         
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			         <title><![CDATA[METHOD AND APPARATUS FOR ALARMING IN A POWER SUPPLY MODULATED SYSTEM]]></title>
			         <link>http://www.patentstorm.us/applications/20120021708/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120021708</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventor:</strong> &nbsp;MURJI, RIZWAN</li></ul>A communication device is presented that has different processors and a power amplifier. One of the processors receives a signal from a monitor and indicates that an alarm exists to a diagnostics module. The other processor uses the envelope signal of the input signal to be amplified and either the signal from the diagnostics module, the monitor or the power amplifier to adjust modulation of the power supply of the power amplifier dependent on the type of alarm. The power supply voltage or ...<br />]]></description>		         
			         <guid isPermaLink="false">20120021708</guid>
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			         <title><![CDATA[RADIO FREQUENCY SIGNAL PROCESSING CIRCUIT AND QUADRATURE POWER AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120021697/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120021697</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventor:</strong> &nbsp;Yang, Wen-Wei</li></ul>A quadrature power amplifier capable of operating in a single-output mode and a multiple-output mode. When operating in the single-output mode, a first quadrature coupler receives a first input signal, and splits and phase-shifts the first input signal into two first split signals. A first power amplifier receives and amplifies one of the two first split signals to generate a first amplified signal. The second power amplifier receives and amplifies the other one of the two first split signals ...<br />]]></description>		         
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			         <title><![CDATA[Method and Apparatus for Improving Efficiency in a Power Supply Modulated System]]></title>
			         <link>http://www.patentstorm.us/applications/20120021695/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120021695</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventor:</strong> &nbsp;MURJI, RIZWAN</li></ul>A radio is presented that has a processor, memory, modulator and a power amplifier. An envelope of a signal to be transmitted is used by the processor to control modulation of the voltage of the power amplifier by the modulator between a desired minimum voltage and a desired maximum voltage. Using the memory, the desired minimum voltage is determined from the desired maximum voltage and these voltages are less than nominal minimum and maximum voltage, respectively. The desired minimum voltage ...<br />]]></description>		         
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			         <title><![CDATA[DOHERTY AMPLIFIER AND SEMICONDUCTOR DEVICE]]></title>
			         <link>http://www.patentstorm.us/applications/20120019326/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019326</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Deguchi, Hiroaki; Ebihara, Kaname</li></ul>A Doherty amplifier includes a carrier amplifier including a first FET, the first FET having a plurality of gate electrodes, and a peaking amplifier including a second FET, the second FET having a plurality of gate electrodes, a gate-to-gate interval of the gate electrodes of the second FET being shorter than a gate-to-gate interval of the first ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019326</guid>
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			         <title><![CDATA[CURRENT-MODE AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120019325/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019325</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Shih, Horng-Yuan; Chen, Wei-Hsien; Juang, Kai-Cheung</li></ul>A current-mode amplifier including an input stage, a feedback circuit and an output stage is provided. The input stage has an input terminal for receiving an input current of the current-mode amplifier. The input stage generates a corresponding inner current in accordance with the input current and a feedback current. The feedback circuit is connected to the input stage. The feedback circuit generates the corresponding feedback current in accordance with the inner current of the input stage. An ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019325</guid>
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			         <title><![CDATA[Amplifier With Improved Input Resistance and Controlled Common Mode]]></title>
			         <link>http://www.patentstorm.us/applications/20120019324/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019324</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;RAJENDRAN, Gireesh; KUMAR, Rakesh; SINGH, Rittu Sachdev</li></ul>An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a first input terminal; a second pair of transistors (the second pair) that defines a second output, each transistor of the second pair having a gate coupled to a second input terminal; a first capacitor coupled to the second output terminal and to the gate of a first transistor of the first pair; a second capacitor coupled to the second ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019324</guid>
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			         <title><![CDATA[CURRENT-MODE AMPLIFIER]]></title>
			         <link>http://www.patentstorm.us/applications/20120019323/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019323</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Shih, Horng-Yuan; Chen, Wei-Hsien; Juang, Kai-Cheung</li></ul>A current-mode amplifier including an input stage, a feedback circuit and an output stage is provided. The input stage has an input terminal for receiving an input current of the current-mode amplifier. The input stage generates a corresponding inner current in accordance with the input current and a feedback current. The feedback circuit is connected to the input stage. The feedback circuit generates the corresponding feedback current in accordance with the inner current of the input stage. An ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019323</guid>
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			         <title><![CDATA[LOW DROPOUT CURRENT SOURCE]]></title>
			         <link>http://www.patentstorm.us/applications/20120019322/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019322</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Silva, Pradeep Charles; Nadimpalli, Praveen Varma; Colles, Joseph Hubert</li></ul>Disclosed is a low dropout current source that includes a first field effect transistor (FET), a second FET having a drain that is an output for an output voltage and an output current, and a third FET, wherein a gate of the first FET is coupled to both a gate of the second FET and a drain of the third FET, and wherein a drain of the first FET is coupled to a source of the third FET. A differential amplifier has an inverting input coupled to the drain of the first FET, a non-inverting input ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019322</guid>
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			         <title><![CDATA[LOW PHASE NOISE BUFFER FOR CRYSTAL OSCILLATOR]]></title>
			         <link>http://www.patentstorm.us/applications/20120019321/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019321</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventor:</strong> &nbsp;Arnborg, Torkel</li></ul>A buffer for converting sinusoidal waves to square waves with reduced phase noise is described herein. The buffer shunts current from the outputs of a differential amplifier during sinusoidal state transition periods at the differential amplifier inputs to increase the finite slope of square wave transition periods of the output square wave. More particularly, a sinusoidal wave having alternating peaks and valleys connected by sinusoidal state transition periods is applied to differential ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019321</guid>
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			         <title><![CDATA[Signal alignment for envelope tracking system]]></title>
			         <link>http://www.patentstorm.us/applications/20120019320/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019320</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventor:</strong> &nbsp;Cummins, Shaun</li></ul>There is disclosed a method for determining the timing misalignment between a power supply and an output in an envelope tracking amplification stage, the method including the steps of: estimating a distortion parameter in the amplification stage; and determining a timing error in dependence on the estimated distortion ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019320</guid>
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			         <title><![CDATA[Amplitude Error De-Glitching Circuit and Method of Operating]]></title>
			         <link>http://www.patentstorm.us/applications/20120019319/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019319</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Tomasz, Martin A.; Vinayak, Vikas; Drogi, Serge F.</li></ul>A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The RF power amplifier system may reduce ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019319</guid>
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			         <title><![CDATA[VARIABLE RESISTER HAVING RESISTANCE VARYING GEOMETRICALLY RATIO AND CONTROL METHOD THEREOF]]></title>
			         <link>http://www.patentstorm.us/applications/20120019318/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019318</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventor:</strong> &nbsp;LEE, Jongwoo</li></ul>Provided is an analog amplifier for amplifying an analog signal and an analog filter, and in particular, an apparatus and method for controlling gain and cutoff frequency of the variable gain amplifier and the variable cutoff frequency filter that is capable of changing the gain and cutoff frequency. The variable resister includes a plurality of resister segments in the variable resister and, when a plurality of resistance candidates for the variable resister are arranged in order of size, the ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019318</guid>
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			         <title><![CDATA[Self-Oscillating Driver Circuit]]></title>
			         <link>http://www.patentstorm.us/applications/20120019317/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019317</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Wiesbauer, Andreas; Giotta, Dario; Bello, David San Segundo; Poctscher, Thomas</li></ul>A self-oscillating driver circuit includes a driver stage, a feedforward path which is coupled to an input of the driver stage, and a feedback path which couples an output of the driver stage to an input of the feedforward path. The feedforward path includes a feedforward filter which is designed as an active filter. In order to prevent an oscillatory state of the driver circuit at an unwanted frequency, it is proposed that an internal state variable of the feedforward filter be monitored and ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019317</guid>
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			         <title><![CDATA[Mixer for Canceling Second-Order Inter-Modulation Distortion and Associated Transconductor Circuit]]></title>
			         <link>http://www.patentstorm.us/applications/20120019304/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120019304</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Hsiao, Shuo Yuan; Chen, Min-Chiao</li></ul>A transconductor circuit used in a mixer for canceling second-order inter-modulation distortion includes a first transistor and a second transistor, of which the base (gate) ends coupled to a first input end and a second input end, for receiving a differential input signal; and a negative feedback circuit, of which the input end coupled to the emitter (source) ends of the first transistor and the second transistor, of which the out end coupled to the base (gate) ends of the first transistor and ...<br />]]></description>		         
			         <guid isPermaLink="false">20120019304</guid>
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			         <title><![CDATA[DIFFERENTIAL AMPLIFIER WITH FUNCTION OF VARIABLE GAIN AND OPTICAL RECEIVER IMPLEMENTED WITH THE SAME]]></title>
			         <link>http://www.patentstorm.us/applications/20120018622/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120018622</li><li><strong>Publication Date:</strong> &nbsp;2012-01-26</li><li><strong>Inventors:</strong> &nbsp;Sawada, Sosaku; SUGIMOTO, Yoshiyuki; Tatsumi, Taizo</li></ul>A differential circuit with a function of a variable gain without shifting the output cross point is disclosed. The differential circuit includes an amplifying stage and a control stage. The amplifying stage includes three units each having a pair of transistors, a pair of load resistors, and a pair of current sources. The second and third units each put between the first unit and the load resistor to bypass the current. The control stage includes two units and two current sources to compensate ...<br />]]></description>		         
			         <guid isPermaLink="false">20120018622</guid>
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			         <title><![CDATA[RF DETECTOR WITH CREST FACTOR MEASUREMENT]]></title>
			         <link>http://www.patentstorm.us/applications/20120013405/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120013405</li><li><strong>Publication Date:</strong> &nbsp;2012-01-19</li><li><strong>Inventors:</strong> &nbsp;Eken, Yalcin Alper; Katzin, Peter</li></ul>An RF detector configured to provide two outputs, one being a function of the true RMS power level of an RF input signal, and the other being a function of the instantaneous/peak power of the RF input signal, normalized to the average power level. The RF detector includes a variable gain detection subsystem including a single detector or detector array that provides a representation of the power level of the RF input signal. The detector or detector array is common to both the RMS power ...<br />]]></description>		         
			         <guid isPermaLink="false">20120013405</guid>
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			         <title><![CDATA[Method and Apparatus for Broadband Input Matching with Noise and Non-Linearity Cancellation in Power Amplifiers]]></title>
			         <link>http://www.patentstorm.us/applications/20120013404/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120013404</li><li><strong>Publication Date:</strong> &nbsp;2012-01-19</li><li><strong>Inventor:</strong> &nbsp;NGAI, Wai Lim</li></ul>A CMOS differential power amplifier having broadband input matching with Noise and Non-linearity Cancellation. The broadband input match is realized by using two “Diode-Connected” NFETs (i.e., N-type Field Effect Transistors). Resulting noise degradation is reduced by using a noise cancellation structure. By using the same structure the disclosed method and apparatus also achieves non-linearity ...<br />]]></description>		         
			         <guid isPermaLink="false">20120013404</guid>
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			         <title><![CDATA[AMPLIFIER CIRCUIT]]></title>
			         <link>http://www.patentstorm.us/applications/20120013403/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120013403</li><li><strong>Publication Date:</strong> &nbsp;2012-01-19</li><li><strong>Inventors:</strong> &nbsp;SAHARA, Ryusuke; UENO, Satoshi; KAWATA, Takahiro</li></ul>An amplifier circuit is configured to be preceded by a single-ended-to-differential translate circuit using a BTL configuration operating at a low voltage and succeeded by amplifiers to amplify output signals VOT and VOB from the single-ended-to-differential translate circuit. The amplifier circuit activates a mute function of the subsequent amplifiers during state transition when the single-ended-to-differential translate circuit turns on. Consequently, the amplifier circuit fixes output ...<br />]]></description>		         
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			         <title><![CDATA[Closed-loop class-d amplifier with modulated reference signal and related method]]></title>
			         <link>http://www.patentstorm.us/applications/20120013402/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120013402</li><li><strong>Publication Date:</strong> &nbsp;2012-01-19</li><li><strong>Inventors:</strong> &nbsp;Jiang, Xicheng; Brooks, Todd L.; Song, Jungwoo; Wang, Minsheng</li></ul>Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal ...<br />]]></description>		         
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			         <title><![CDATA[POWER AMPLIFIER WITH SELECTABLE LOAD IMPEDANCE AND METHOD OF AMPLIFYING A SIGNAL WITH SELECTABLE LOAD IMPEDANCE]]></title>
			         <link>http://www.patentstorm.us/applications/20120013401/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120013401</li><li><strong>Publication Date:</strong> &nbsp;2012-01-19</li><li><strong>Inventors:</strong> &nbsp;JEON, Moon-Suk; KOO, Chan Hoe; LEE, Hyung Bin; JUNG, Sang Hwa</li></ul>A device includes: a power amplifier, including a supply voltage terminal, an input port and an output port, and the power amplifier being configured to receive a supply voltage at the supply voltage terminal, an input signal through the input port, to amplify the received input signal, and to output an amplified output signal through the output port; a variable impedance matching circuit having an input terminal connected to the output port of the power amplifier, and having an output terminal ...<br />]]></description>		         
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			         <title><![CDATA[Current Control Circuit, Class AB Operational Amplifier System and Current Control Method]]></title>
			         <link>http://www.patentstorm.us/applications/20120013400/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120013400</li><li><strong>Publication Date:</strong> &nbsp;2012-01-19</li><li><strong>Inventors:</strong> &nbsp;Chang, Ming-Hung; Lin, Che-Hung</li></ul>A current control circuit for controlling a bias current of a class AB operational amplifier includes: a low current source, for generating a low bias current; a high current source, for generating a high bias current, which is greater than the low bias current; and a comparing and selecting unit, coupled to an output terminal of the class AB operational amplifier, for selecting one of the low bias current and the high bias current to output as the bias current according to an output voltage of ...<br />]]></description>		         
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			         <title><![CDATA[AUTOMATIC GAIN CONTROL CIRCUIT AND AUTOMATIC GAIN CONTROL METHOD]]></title>
			         <link>http://www.patentstorm.us/applications/20120013399/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120013399</li><li><strong>Publication Date:</strong> &nbsp;2012-01-19</li><li><strong>Inventor:</strong> &nbsp;Huang, Kung-Piao</li></ul>An automatic gain control method includes receiving a sequence of multiple digital data, and calculating a plurality of signal values corresponding to the respective voltage values of the digital data, such as multiple peak-to-peak voltage values or power values, so as to optimize a gain according to variations in the output values. The gain optimization includes updating a reference value according to the signal values. If the reference value is less than a minimum threshold, the gain is ...<br />]]></description>		         
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