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		    <title>PatentStorm ->  Applications -> Miscellaneous active electrical nonlinear devices, circuits, and systems</title>
		    <link>http://www.patentstorm.us/rss/class/applications/rss-327.xml</link>
		    <description>Recent patent applications filings in USPTO Class 327 Miscellaneous active electrical nonlinear devices, circuits, and systems.</description>
		    <pubDate>Thu, 9 Feb 2012 15:03:26</pubDate>
		    <managingEditor>patents@patentstorm.us</managingEditor>
		    <language>en</language><item>
			         <title><![CDATA[Timing control circuit]]></title>
			         <link>http://www.patentstorm.us/applications/20120036335/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120036335</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;van Winkelhoff, Nicolaas Klarinus Johannes; Aghetti, Bastien Jean Claude</li></ul>A timing control circuit comprises at least three current control units coupled in parallel between a first circuit and a second circuit node. The current control units each have an active mode and an inactive mode. The current control units are responsive to a timing trigger event to pass current whose magnitude is dependent on how many of the current control units are in the active mode. The current control units comprise a plurality of groups. Current control units within a same group are ...<br />]]></description>		         
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			         <title><![CDATA[SEMICONDUCTOR DEVICE]]></title>
			         <link>http://www.patentstorm.us/applications/20120033506/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120033506</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Furutani, Kiyohiro; Matsui, Yoshinori</li></ul>A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal ...<br />]]></description>		         
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			         <title><![CDATA[OPERATIONAL AMPLIFIER CIRCUIT, SIGNAL DRIVER, DISPLAY DEVICE, AND OFFSET VOLTAGE ADJUSTING METHOD]]></title>
			         <link>http://www.patentstorm.us/applications/20120032944/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032944</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;KOJIMA, Tomokazu</li></ul>Provided is an operational amplifier circuit including a Rail-to-Rail differential amplifier including: first and second differential transistors forming a first differential pair; and third and fourth differential transistors forming a second differential pair, wherein each of the first and second differential transistors is an n-type MOS transistor, each of the third and fourth differential transistors is a p-type MOS transistor, and the operational amplifier circuit further includes: a first ...<br />]]></description>		         
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			         <title><![CDATA[OUTPUT CIRCUIT, DATA DRIVER AND DISPLAY DEVICE]]></title>
			         <link>http://www.patentstorm.us/applications/20120032939/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032939</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;TSUCHI, Hiroshi</li></ul>An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit. The third power supply voltage is intermediate between the first and second power supply voltages. The differential amplifier circuit includes, between the first and second power supplies, a differential input stage, first and second current mirror and first and second junction circuits. The output amplifier circuit includes first and second transistors connected between the first and ...<br />]]></description>		         
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			         <title><![CDATA[SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, AND OPERATING CLOCK ADJUSTMENT METHOD THEREFOR]]></title>
			         <link>http://www.patentstorm.us/applications/20120032824/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032824</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;YOSHIOKA, Masato</li></ul>A successive approximation register analog-to-digital converter includes: a digital-to-analog converter to generate an analog voltage based on an input voltage sampled in accordance with a sampling clock and a digital code; a comparator to receive the analog voltage; a controller to generate the digital code based on an output of the comparator; a delay circuit to delay a signal based on the output of the comparator and to feed back the delayed signal to a reset terminal of the comparator; an ...<br />]]></description>		         
			         <guid isPermaLink="false">20120032824</guid>
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			         <title><![CDATA[Systems and Methods of Ripple Reduction in a DC/DC Converter]]></title>
			         <link>http://www.patentstorm.us/applications/20120032748/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032748</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Li, Xuening; Wu, Wenkai; Chen, Hal; Zhu, Weidong</li></ul>Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width ...<br />]]></description>		         
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			         <title><![CDATA[Frequency-Coupled LCVCO]]></title>
			         <link>http://www.patentstorm.us/applications/20120032745/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032745</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Nedovic, Nikola</li></ul>In one embodiment, a method includes generating, by a LCVCO, a first signal having a first phase based on a resonant frequency of a first LC tank; generating, by a second LCVCO, a second periodic signal having a second phase based on a resonant frequency of a second LC tank; determining a phase offset between the first LC tank and the second LC tank based on the first and second signals; generating a first output signal and a second output signal based on the determined phase offset; and ...<br />]]></description>		         
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			         <title><![CDATA[REDUCING COUPLING COEFFICIENT VARIATION BY USING CAPACITORS]]></title>
			         <link>http://www.patentstorm.us/applications/20120032735/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032735</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Reisner, Russ; Li, Yang; Zhu, Xuanang; Prikhodko, Dmitri; Hoang, Dinhphuoc V.; Zhang, Guohao; Guo, Jiunn-Sheng; Scoles, Bradley D.; Viveiros, JR., David</li></ul>A coupler is presented that has high-directivity and low coupling coefficient variation. The coupler includes a first trace associated with a first port and a second port. The first port is configured substantially as an input port and the second port is configured substantially as an output port. The coupler further includes a second trace associated with a third port and a fourth port. The third port is configured substantially as a coupled port and the fourth port is configured substantially ...<br />]]></description>		         
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			         <title><![CDATA[INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE]]></title>
			         <link>http://www.patentstorm.us/applications/20120032734/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032734</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;DO, Chang-Ho</li></ul>An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external ...<br />]]></description>		         
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			         <title><![CDATA[SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SUPPLY VOLTAGE SUPERVISOR]]></title>
			         <link>http://www.patentstorm.us/applications/20120032733/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032733</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;NEGORO, Takaaki</li></ul>A semiconductor integrated circuit device includes a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and ...<br />]]></description>		         
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			         <title><![CDATA[HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING]]></title>
			         <link>http://www.patentstorm.us/applications/20120032732/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032732</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Lee, Roger; Xiao, DeYuan; Chen, Guo Qing</li></ul>A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a ...<br />]]></description>		         
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			         <title><![CDATA[CHARGE PUMP DOUBLER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032731/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032731</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;HUANG, Ming-Chieh; SWEI, Yuwen; LIN, Chih-Chang; CHERN, Chan-Hong; YANG, Tien-Chun</li></ul>An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is ...<br />]]></description>		         
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			         <title><![CDATA[SEMICONDUCTOR INTEGRATED DEVICE]]></title>
			         <link>http://www.patentstorm.us/applications/20120032730/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032730</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Koyama, Jun</li></ul>To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel ...<br />]]></description>		         
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			         <title><![CDATA[METHOD AND APPARATUS FOR PROTECTING TRANSISTORS]]></title>
			         <link>http://www.patentstorm.us/applications/20120032729/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032729</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Achleitner, Günter; Pammer, Walter; Pirchenfellner, Jürgen; Holzinger, Stephan</li></ul>The invention relates to a method and to an apparatus for protecting transistors (S<b>1</b>, S<b>3</b>; S<b>2</b>, S<b>4</b>) arranged in at least one path, wherein transistors (S<b>1</b>, S<b>3</b>; S<b>2</b>, S<b>4</b>) connected in series to which an input voltage (Ue) is applied are arranged in a path (<b>2</b>), and the transistors (S<b>1</b>, S<b>3</b>; S<b>2</b>, S<b>4</b>) of a path are alternately switched between a conductive state and a blocking state in order to generate an output ...<br />]]></description>		         
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			         <title><![CDATA[AUTO-OPTIMIZATION CIRCUITS AND METHODS FOR CYCLICAL ELECTRONIC SYSTEMS]]></title>
			         <link>http://www.patentstorm.us/applications/20120032728/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032728</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Coleman, Charles; Wittenbreder, JR., Ernest H.; Ochi, Sam Seiichiro; Yedevelly, Yeshoda</li></ul>Methods, systems, and devices are described for an adjustment module that interacts with a parameter detection module to provide a threshold value for initiating switching of a switching module in a cyclical electronic system. Aspects of the present disclosure provide a switching module used in conjunction with an inductor that is coupled with the switching module. The threshold voltage for switching the switching module may be adjusted to provide switching at substantially zero volts while ...<br />]]></description>		         
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			         <title><![CDATA[CIRCUIT BREAKER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032727/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032727</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Callanan, Robert J.</li></ul>A circuit breaker is provided that includes primary and secondary paths that extend between first and second terminals. The primary path extends between the first and second terminals and through a first switch. The secondary path extends between the first and second terminals and through the second switch and a semiconductor switching element. During normal operation, a control system maintains the first and second switches in closed position and the semiconductor switching element in blocking ...<br />]]></description>		         
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			         <title><![CDATA[POWER SUPPLY SELECTION/DETECTION CIRCUIT]]></title>
			         <link>http://www.patentstorm.us/applications/20120032726/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032726</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;NISHIGATA, Yoshitaka</li></ul>A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power supply and another end connected to the main power supply, a first voltage detector to receive a voltage of the external power supply and detect a voltage of the external power supply, a second voltage detector to detect a voltage between the ends of the resistance element, and a switch connected between ...<br />]]></description>		         
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			         <title><![CDATA[POWER MODULE]]></title>
			         <link>http://www.patentstorm.us/applications/20120032725/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032725</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;HIYAMA, Kazuaki</li></ul>A power module comprises: first and second terminals; first and second switching elements having a first electrode and a second electrode which is connected to the second terminal; first and second wirings respectively connecting the first electrodes of the first and second switching elements to the first terminal; and a third wiring directly connecting the first electrode of the first switching element to the first electrode of the second switching element, wherein parasitic inductances of the ...<br />]]></description>		         
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			         <title><![CDATA[CIRCUIT AND METHOD FOR GENERATING PUMPING VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME]]></title>
			         <link>http://www.patentstorm.us/applications/20120032724/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032724</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Kwon, Jae Kwan</li></ul>A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level ...<br />]]></description>		         
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			         <title><![CDATA[SYSTEM AND METHOD FOR SIGNAL LIMITING]]></title>
			         <link>http://www.patentstorm.us/applications/20120032723/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032723</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Moloudi, Shervin</li></ul>A method for processing a signal with a corresponding noise profile includes analyzing spectral content of the noise profile, filtering at least one noise harmonic within the signal based on the analyzed spectral content, and limiting the filtered signal. The noise profile may include a phase noise profile. The signal may include a sinusoidal signal and/or a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may ...<br />]]></description>		         
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			         <title><![CDATA[Offset Calibration for Amplifiers]]></title>
			         <link>http://www.patentstorm.us/applications/20120032722/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032722</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;MULDER, Jan</li></ul>An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (V<sub>IN</sub><sup>+</sup>), a negative differential input (V<sub>IN</sub><sup>−</sup>), a positive differential output (V<sub>OUT</sub><sup>+</sup>), and a negative differential output (V<sub>OUT</sub><sup>−</sup>). The voltage ...<br />]]></description>		         
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			         <title><![CDATA[CLOCK TREE FOR PULSED LATCHES]]></title>
			         <link>http://www.patentstorm.us/applications/20120032721/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032721</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;MALLEM, Yahia; GIROUD, Mickael; JURE, Lionel</li></ul>The invention concerns a computer implemented method of circuit conception of a clock tree (<b>200</b>) comprising: a plurality of pulse generators (<b>202</b>) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (<b>204</b>) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of ...<br />]]></description>		         
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			         <title><![CDATA[METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES]]></title>
			         <link>http://www.patentstorm.us/applications/20120032720/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032720</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;SOFER, SERGEY</li></ul>A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a ...<br />]]></description>		         
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			         <title><![CDATA[ELECTRONIC CIRCUIT AND METHOD FOR OPERATING A MODULE IN A FUNCTIONAL MODE AND IN AN IDLE MODE]]></title>
			         <link>http://www.patentstorm.us/applications/20120032719/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032719</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Priel, Michael; Rozen, Anton; Seidenwar, Yaakov</li></ul>A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the ...<br />]]></description>		         
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			         <title><![CDATA[Digital Phase Lock System with Dithering Pulse-Width-Modulation Controller]]></title>
			         <link>http://www.patentstorm.us/applications/20120032718/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032718</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;CHAN, Chi Fat; LIN, Chien-Wei; CHUNG, Gordon</li></ul>A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference ...<br />]]></description>		         
			         <guid isPermaLink="false">20120032718</guid>
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			         <title><![CDATA[POWER-ON RESET CIRCUIT]]></title>
			         <link>http://www.patentstorm.us/applications/20120032717/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032717</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Suzuki, Hajime; Miura, Satoshi</li></ul>When the value of a power supply voltage (VDD) becomes a first threshold value or higher, a first start-up circuit (<b>20</b>) causes a band gap reference circuit (<b>10</b>) to start a stable operation and a first voltage value (V<sub>A</sub>) is output from the band gap reference circuit (<b>10</b>). When the value of the power supply voltage becomes a second threshold value or higher which is greater than the first threshold, a second start-up circuit (<b>40</b>) turns on a PMOS transistor ...<br />]]></description>		         
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			         <title><![CDATA[Initializing Components of an Integrated Circuit]]></title>
			         <link>http://www.patentstorm.us/applications/20120032716/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032716</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Nguyen, Giang Chau; Dinkjian, Robert Michael; Rakes, James Mitchell</li></ul>Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one ...<br />]]></description>		         
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			         <title><![CDATA[HIGH-SPEED FREQUENCY DIVIDER AND A PHASE LOCKED LOOP THAT USES THE  HIGH-SPEED FREQUENCY DIVIDER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032715/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032715</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Subburaj, Karthik; K, Dhanya</li></ul>A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality ...<br />]]></description>		         
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			         <title><![CDATA[OUTPUT DRIVER DEVICE FOR INTEGRATED CIRCUIT]]></title>
			         <link>http://www.patentstorm.us/applications/20120032714/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032714</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Shibayama, Naoya; SHIMAZAKI, Yoji</li></ul>A driver device drives a load circuit by a common output signal from a first driver transistor and a second driver transistor. The driver device includes a first pre-driver unit that outputs a first driver control signal to the first driver transistor in response to the input signal; and a second pre-driver unit that outputs a second driver control signal to the second driver transistor in response to the input signal. The first pre-driver unit controls the first driver control signal in such a ...<br />]]></description>		         
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			         <title><![CDATA[Semiconductor Device and Power Supply Unit Utilizing the Same]]></title>
			         <link>http://www.patentstorm.us/applications/20120032713/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032713</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;KITAGAWA, Atsushi</li></ul>A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest ...<br />]]></description>		         
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			         <title><![CDATA[HIGH TEMPERATURE OPERATING PACKAGE AND CIRCUIT DESIGN]]></title>
			         <link>http://www.patentstorm.us/applications/20120032712/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032712</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Lang, Dennis; Thornton, Neill</li></ul>The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second ...<br />]]></description>		         
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			         <title><![CDATA[SYSTEM AND METHOD FOR PRE-CHARGING A CURRENT MIRROR]]></title>
			         <link>http://www.patentstorm.us/applications/20120032711/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032711</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Hageman, Michael L.; Fisher, Robert Michael; Ripley, David S.</li></ul>A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current ...<br />]]></description>		         
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			         <title><![CDATA[SEMICONDUCTOR DEVICE DRIVING UNIT AND METHOD]]></title>
			         <link>http://www.patentstorm.us/applications/20120032710/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032710</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Tsukada, Yoshinari</li></ul>A semiconductor device (<b>11</b>) having a switching function of being turned on or off according to a voltage (Vge) of a driving signal supplied to a gate thereof is driven by generating a feedback voltage (V<sub>FE</sub>) based on a time change (dI/dt) of a collector current (Ic) of the semiconductor device (<b>11</b>) and applying the feedback voltage (V<sub>FE</sub>) as part of the voltage (Vge) of the driving signal when the semiconductor device (<b>11</b>) is switched from on to ...<br />]]></description>		         
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			         <title><![CDATA[SEMICONDUCTOR DEVICE DRIVING UNIT AND METHOD]]></title>
			         <link>http://www.patentstorm.us/applications/20120032709/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032709</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Saotome, Koji; Tsukada, Yoshinari; Goto, Masatoshi; Takeuchi, Yusuke</li></ul>A turn-off feedback unit (<b>23</b>OFF) of a semiconductor device driving unit generates a feedback voltage as part of a voltage of a drive signal for establishing electrical continuity or disconnection in a bus according to a temporal variation of a collector current of a first semiconductor device (<b>11</b>U) when the first semiconductor device (<b>11</b>U) is turned off from on. A turn-on feedback unit (<b>23</b>ON) generates the feedback voltage according to a commutation current flowing ...<br />]]></description>		         
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			         <title><![CDATA[GATE DRIVER POWER AND CONTROL SIGNAL TRANSMISSION CIRCUITS AND METHODS]]></title>
			         <link>http://www.patentstorm.us/applications/20120032708/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032708</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Coleman, Charles</li></ul>Methods, systems, and devices are described for both power and control signal transmission through a single coupled inductor. A current driver generates a cyclical current signal on a primary winding of a coupled inductor, to induce a voltage signal at the secondary winding corresponding to the cyclical current signal. A rectifier module is coupled with the secondary winding and configured to rectify the signal induced at the secondary winding. A control timing signal module is coupled with the ...<br />]]></description>		         
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			         <title><![CDATA[Load driving device]]></title>
			         <link>http://www.patentstorm.us/applications/20120032707/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032707</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Nakahara, Akihiro</li></ul>A load driving device includes a power supply terminal, a ground terminal, an output terminal coupled to a load, an output transistor coupled between the power supply and output terminals, a driver circuit supplying a first control signal to turn on the output transistor and a second control signal to turn off the output transistor, a discharge circuit coupled between the control terminal of the output transistor and the output terminal, a compensation circuit that turns on when a potential of ...<br />]]></description>		         
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			         <title><![CDATA[MULTI-CHIP PACKAGE]]></title>
			         <link>http://www.patentstorm.us/applications/20120032706/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032706</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;KIM, Kyoung Nam; Shin, Beom Ju</li></ul>A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being ...<br />]]></description>		         
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			         <title><![CDATA[Device for Detecting Pulsed Signals Comprising a Function for Detecting Tangling of Pulses]]></title>
			         <link>http://www.patentstorm.us/applications/20120032705/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032705</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Letellier, Frankie; Boulanger, Emilie</li></ul>A device for detecting non-phase-modulated pulsed signals or sequences of pulses of a determined frequency includes means for detecting tangling of pulses, at least one amplifier receiving a radiofrequency signal, and restoring at least one first signal representative of the envelope of the input signal, and a second normalized signal. A phase jump estimation module includes means for estimating the phase of the radiofrequency signal, means for evaluating a phase jump, the presence of pulse ...<br />]]></description>		         
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			         <title><![CDATA[REDUCING SHOOT-THROUGH IN A SWITCHING VOLTAGE REGULATOR]]></title>
			         <link>http://www.patentstorm.us/applications/20120032657/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032657</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Dequina, Noel B.</li></ul>Methods, apparatuses, and devices for a voltage regulator are provided. In certain examples, a method for preventing shoot-through in a voltage regulator includes determining whether an output stage for a voltage regulator is operating in a continuous-conduction mode (CCM) or a discontinuous conduction mode (DCM); and setting the voltage regulator in one of adaptive dead time mode and programmable dead time mode based on whether the output stage is operating in CCM or ...<br />]]></description>		         
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			         <title><![CDATA[CIRCUIT FOR GENERATING A CLOCK SIGNAL FOR INTERLEAVED PFC STAGES AND METHOD THEREOF]]></title>
			         <link>http://www.patentstorm.us/applications/20120032652/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032652</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;Turchi, Joel; Conseil, Stéphanie</li></ul>A method and circuit for generating a clock signal. A power factor correction circuit has n channels operating out of phase and independently. The circuit is able to generate a clock signal for each channel according to the current cycle duration of each ...<br />]]></description>		         
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			         <title><![CDATA[PROXIMITY DETECTION CIRCUIT FOR ON-BOARD VEHICLE CHARGER]]></title>
			         <link>http://www.patentstorm.us/applications/20120032634/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120032634</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventor:</strong> &nbsp;Cavanaugh, William</li></ul>A proximity detection circuit suitable for use with an on-board vehicle charger, such as but not limited to the type of charges used within hybrid and hybrid electric vehicles, to facilitate current conservation during period of time when it is unnecessary or otherwise undesirable for the on-board charger to test for connection of a cordset or other connection used to connect the on-board charger to a charging station or other current ...<br />]]></description>		         
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			         <title><![CDATA[APPARATUS AND METHOD FOR CONTROLLING TEMPERATURE ON A COOKING APPLIANCE]]></title>
			         <link>http://www.patentstorm.us/applications/20120031893/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120031893</li><li><strong>Publication Date:</strong> &nbsp;2012-02-09</li><li><strong>Inventors:</strong> &nbsp;COX, Patrick Ryan; Lepie, David; Gawron, SR., Gregory Francis</li></ul>An apparatus and a method for measuring temperature in a cooking appliance, both of which utilize a circuit for reading an input from a thermal resistive device. By including a processor and an amplifier in the circuit, embodiments reduce the number of processor pins required to modify the amplified input arising from the amplifier. In one embodiment, the processor utilizes a single processor pin, through which is distributed a control output corresponding to the input and modifying the ...<br />]]></description>		         
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			         <title><![CDATA[TRIGGER CIRCUIT FOR LOW-POWER STRUCTURAL HEALTH MONITORING SYSTEM]]></title>
			         <link>http://www.patentstorm.us/applications/20120029842/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120029842</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;ZHANG, Chang</li></ul>A trigger circuit for use with a structural health monitoring system. To save power, a structural health monitoring system is programmed with a sleep mode and a wake, or operational, mode. In its operational mode, the structural health monitoring system can perform its usual tasks, e.g. monitoring a structure and determining its structural health. In sleep mode, many functions are suspended, so that the system requires less power. The trigger circuit wakes the system when the sensors of the ...<br />]]></description>		         
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			         <title><![CDATA[Modular Frequency Divider and Mixer Configuration]]></title>
			         <link>http://www.patentstorm.us/applications/20120027121/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120027121</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Uehara, Gregory; Gerna, Danilo; Dal Toso, Stefano</li></ul>A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of the plurality of second frequency dividers includes a second plurality of components and is configured to divide the input frequency of the input signal to generate a second ...<br />]]></description>		         
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			         <title><![CDATA[METHOD AND DEVICE FOR GENERATING ULTRA WIDE BAND PULSES]]></title>
			         <link>http://www.patentstorm.us/applications/20120027050/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120027050</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;Bourdel, Sylvain; Vauche, Rémi</li></ul>The disclosure relates to a method for generating UWB waveforms, each comprising a sequence of pulses, the method comprising: generating consecutive elementary pulses having durations corresponding to setpoint durations and a constant amplitude, amplifying each elementary pulse separately as a function of a respective setpoint amplitude, and combining the amplified elementary pulses to obtain a waveform successively comprising each of the amplified alternately positive and negative, elementary ...<br />]]></description>		         
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			         <title><![CDATA[INTEGRATED CIRCUITS FOR PROVIDING CLOCK PERIODS AND OPERATING METHODS THEREOF]]></title>
			         <link>http://www.patentstorm.us/applications/20120026820/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120026820</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventors:</strong> &nbsp;HUANG, Ming-Chieh; PU, Chiang; CHERN, Chan-Hong</li></ul>An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is ...<br />]]></description>		         
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			         <title><![CDATA[Low Cost Testing and Sorting of Integrated Circuits]]></title>
			         <link>http://www.patentstorm.us/applications/20120026817/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120026817</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;STEWART, Roger G.</li></ul>Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second ...<br />]]></description>		         
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			         <title><![CDATA[Method and Apparatus For Use In Monitoring Operation of Electrical Switchgear]]></title>
			         <link>http://www.patentstorm.us/applications/20120026630/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120026630</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;Sutherland, Peter E.</li></ul>An instrument transformer includes a current transformer configured to be coupled to a load, and to generate an analog signal that is proportional to a current flowing through the load. The instrument transformer also includes a protection module and a digitizer module that is coupled to the current transformer. The digitizer module is configured to receive an input signal that is proportional to the analog signal and to convert the input signal to a digital signal. The digitizer module ...<br />]]></description>		         
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			         <title><![CDATA[OVER-DRIVABLE OUTPUT BUFFER, SOURCE DRIVER CIRCUIT HAVING THE SAME, AND METHODS THEREFOR]]></title>
			         <link>http://www.patentstorm.us/applications/20120026152/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120026152</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;CHUNG, Kyu-young</li></ul>Provided is an output buffer for a source driver circuit which receives an external buffer input signal and generates a buffer output signal having a predetermined target voltage, the output buffer including: an over-driving controller configured to generate a pair of first internal buffer input signals and a pair of second internal buffer input signals for an over-driving operation, based on a first over-driver enable signal and a second over-driver enable signal, the first and second ...<br />]]></description>		         
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			         <title><![CDATA[A/D CONVERTER USING ISOLATION SWITCHES]]></title>
			         <link>http://www.patentstorm.us/applications/20120026027/description.html</link>
			         <description><![CDATA[<ul><li><strong>Application Number:</strong> &nbsp;20120026027</li><li><strong>Publication Date:</strong> &nbsp;2012-02-02</li><li><strong>Inventor:</strong> &nbsp;Steensgaard-Madsen, Jesper</li></ul>In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the ...<br />]]></description>		         
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