U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Process for forming a thin oxide layer

Patent RE38674 Issued on December 21, 2004.

Patent References

3556879

Method for use in the manufacture of semiconductor devices
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Issued on: 07/03/1979
Inventor: Gluck

Method of removing impurity metals from semiconductor devices
Patent #: 4231809
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Inventor: Schmidt

Method of passivating a semiconductor device with a multi-layer passivant system by thermally growing a layer of oxide on an oxygen doped polycrystalline silicon layer
Patent #: 4344985
Issued on: 08/17/1982
Inventor: Goodman ,   et al.

MOS Isolation processing
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Issued on: 11/12/1985
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Method of manufacturing a semiconductor device, in which a silicon wafer is provided at its surface with field oxide regions
Patent #: 4906595
Issued on: 03/06/1990
Inventor: van der Plas, et al.

Semiconductor device having an improved wiring pattern
Patent #: 4994894
Issued on: 02/19/1991
Inventor: Nakayama, ;, , , --> Nakayama

Method for forming a thin layer on a semiconductor substrate
Patent #: 5028560
Issued on: 07/02/1991
Inventor: Tsukamoto, et al.

Thin oxide structure and method
Patent #: 5057463
Issued on: 10/15/1991
Inventor: Bryant, et al.

Apparatus for forming a thin film on surface of semiconductor substrate Patent #: 5174881
Issued on: 12/29/1992
Inventor: Iwasaki, et al.

Inventors

Assignee

Application

No. 08528188 filed on 09/14/1995

US Classes:

438/773, In atmosphere containing water vapor (i.e., wet oxidation)438/774, In atmosphere containing halogen438/762, At least one layer formed by reaction with substrate438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)438/287, Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound438/452, Plural oxidation steps to form recessed oxide257/E21.193, On single crystalline silicon (EPO)257/E21.285Of silicon (EPO)

Examiners

Primary: Booth, Richard A.

Attorney, Agent or Firm

Foreign Patent References

  • 2172746 GB 09/01/1981
  • 62-235740 JP 10/01/1987
  • 3147369 JP 06/01/1991

International Classes

H01L 2131
H01L 21469

Abstract

A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 Å. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 Å. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 Å, a composite oxide stack is used which comprises 40-90 Å of pad oxide formed using the above novel process, and 60-200 Å of deposited oxide.

Other References

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  • Ghandhi, “VLSI Fabrication Principles”, 1983, pp. 385-388, John Wiley and Sons, 1983.*
  • C. Wei, Y. Nissan-Cohen, and H. Woodbury; “Evaluation of 850° C. Wet Oxideee As The Gate Dielectric In A 0.8 μm CMOS Process”; IEEE Transactions On Electron Devices; vol. 38, No. 11 (Nov. 1991); pp. 2433-2441.*
  • R.G. Cosway and C.E. Wu; Comparison Of Thin Thermal SiO2 Grown Using HCl and 1,1,1 Trichloroethane (TCA); Journal Of The Electrochemical Society; Solid-State Science and Technology; vol. 132, No. 1, (Jan. 1985); pp. 151-154.*
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  • S. Wolf; “Silicon Processing For The VLSI Era”; vol. 2, Chapter 2, 1990.*
  • S. Wolf and R.N. Tauber; “Silicon Processing For The VLSI Era”; vol. 1, Chapter 7, 1986; pp. 215-216.*
  • Deal, B.; “The Oxidation . . . and Steam”; J. Electochem Society; vol. 110, No. 6, Jun. 1968; pp. 527-533.*
  • Gdula, R.; “Composite Dielectric Layer”; IBM Tech. Disc. Bull., vol. 14, No. 9, Feb. 1972; p. 2609.*
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  • Kanigaki, Y.; “Thermal Oxidation . . . by Nitrogen”; Appl. Phys.; vol. 48, No. 7, Jul. 1977; pp. 2891-2896.*
  • Wolf et al., “Silicon Processing for the VLSI Era vol. 1: Process Technology”, Lattice Press, pp. 215-216, 1986.*
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