Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices

Patent 8214575 Issued on July 3, 2012. Estimated Expiration Date:

December 21, 2030. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Full Text

Patent References

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Inventors

Assignee

Rambus Inc.

Application

No. 12975313 filed on 12/21/2010

US Classes:

710/305Bus interface architecture

Examiners

Primary: Myers, Paul

Attorney, Agent or Firm

MORGAN, LEWIS & BOCKIUS LLP

Foreign Patent References

0015583 EP 09/01/1980
410769 EP 01/01/1991
0657797 EP 06/01/1995
0855653 EP 07/01/1998
2170047 GB 07/01/1986
2237691 GB 05/01/1991
59004204 JP 01/01/1984
04068561 JP 03/01/1992
08221980 JP 08/01/1996

International Class

G06F 13/42

Abstract

A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.

Other References

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