Patent ReferencesBurst broadcasting on a peripheral component interconnect bus System and method for converting VXI bus cycles to PCI burst cycles Memory and graphics controller which performs pointer-based display list video refresh operations System for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transaction System for implementing an adaptive burst length for burst mode transactions of a memory by monitoring response times for different memory regions Burst-configurable data bus Synchronous memory system with automatic burst mode switching as a function of the selected bus master Network interface with power conservation using dynamic clock control Method and apparatus for improving processing throughput in a video graphics system DRAM supporting different burst-length accesses without changing the burst length setting in the mode register InventorAssigneeApplicationNo. 12039986 filed on 02/29/2008US Classes:710/110Bus master/slave controllingExaminersPrimary: Misiura, BrianAttorney, Agent or FirmInternational ClassesG06F 13/00G06F 13/14 G06F 1/00 AbstractAn electronic apparatus to allow data to be sent and received between a master unit and a slave unit through a peripheral component interconnect (PCI) bus is provided. Each of the master unit and the slave unit comprises a data interface having a plurality of pins through which request data is sent to and received from an external device, and additional pins through which size information of the request data is sent to and received from the external device. If the master unit sends address information and the size information of the request data to the slave unit through the plurality of pins and the additional pins, the slave unit processes data of an address corresponding to the received address information according to size corresponding to the size information.Other References
Field of SearchBurst data transfer | |