Buffered DRAM
January 4, 2028. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesClock vernier adjustment Memory system including a point-to-point linked memory subsystem Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same Buffering and interleaving data transfer between a chipset and memory modules Synchronous dynamic random access memory device having memory command cancel function Memory module Patent #: 7072201 InventorAssigneeApplicationNo. 12006599 filed on 01/04/2008US Classes:365/189.05Having particular data buffer or latch , 365/189.17ExaminersPrimary: Luu, Pho MAssistant: Bui, Thao Attorney, Agent or FirmInternational ClassG11C 7/10AbstractA buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further coupled to receive address and command signals. If data access is directed to a second DRAM, the buffer buffers the data and strobe signals for access by the second DRAM. If data access is directed to the buffered DRAM the buffer buffers the data and strobe signals for access by the DRAM memory cell. | |
