Method and system for utilizing a single PLL to clock an array of DDFS for multi-protocol applications
Patent 8014422 Issued on September 6, 2011. Estimated Expiration Date: September 28, 2027. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Methods and systems for utilizing a single PLL to clock an array of DDFS for multi-protocol applications are disclosed. Aspects of one method may include generating a first signal for use in generating a plurality of local oscillator (LO) signals. The first signal may be communicated to a plurality of LO generators. Each of the LO signals may be generated independently of each other by a corresponding one of the LO generators. Each of the LO signals may be communicated to one or more mixers, where each mixer may perform down-conversion or up-conversion. A LO generator may utilize, for example, a DDFS or a digital delay circuit. A frequency of a LO signal may be varied by adjusting a divide factor for a divider that generates a reference clock for the DDFS or for a divider that generates a second signal used for mixing with a signal generated by the DDFS. The LO signal frequency may also be varied by adjusting frequency control words received by a DDFS.