Patent 7868606 Issued on January 11, 2011. Estimated Expiration Date: February 15, 2028. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Improved process variation sensors and techniques are disclosed, wherein both global and local variations associated with transistors on an integrated circuit can be monitored. For example, respective circuits for sensing a global process variation, a local process variation between neighboring negative-channel type transistors, and a local process variation between neighboring positive-channel type transistors are disclosed. Further, in one example, a method for sensing a process variation associated with transistors on an integrated circuit includes providing at least one process variation sensor on the integrated circuit, the process variation sensor comprising a sensing portion including one or more transistors and a loading and amplification portion including one or more transistors, and operating the one or more transistors of the sensing portion and the one or more transistors of the loading and amplification portion in a subthreshold region of transistor operation such that when a threshold voltage of at least one of the transistors changes, a process variation is sensed.
Other References
N. Jayakumar et al., “A Self-Adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage Currents,” Jun. 2005, DAC, pp. 43-46, California.
M. Bhushan et al., “Ring Oscillators for CMOS Process Tuning and Variability Control,” IEEE Transactions on Semiconductor Manufacturing, Feb. 2006, pp. 10-18, vol. 19, No. 1.
Chris H. Kim, “Self Calibrating Circuit Design for Variation Tolerant VLSI Systems,” Proceedings of the 11th IEEE International On-Line Testing Symposium, (IOLTS), Jul. 2005, pp. 1-6.
M.M. Griffin et al., “A Process-Independent, 800-MB/s, DRAM Byte-Wide Interface Featuring Command Interleaving and Concurrent Memory Operation,” IEEE Journal of Solid-State Circuits, Nov. 1998, pp. 1741-1751, vol. 33, No. 11.
T. Kuroda et al. “A 0.9V 150 MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme,” ISSCC, Feb. 1996, pp. 166-168.