Patent ReferencesError management processes for flash EEPROM memory arrays Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same Reversibly expandable structures having polygon links Data management for multi-bit-per-cell memories Method and structure for efficient data verification operation for non-volatile memories Non-volatile semiconductor memory device Flash memory device having multi-level cell and reading and programming method thereof Multi-level caching in data storage devices Patent #: 7099993 InventorAssigneeApplicationNo. 11938603 filed on 11/12/2007US Classes:365/189.05Having particular data buffer or latchExaminersPrimary: Dinh, SonAttorney, Agent or FirmForeign Patent References
International ClassG11C 7/00AbstractA method for programming a flash memory device including a plurality of memory cells, each storing multi-bit data, includes reading data from selected memory cells. An error of the read data is detected and corrected. Input program data is programmed into the selected memory cells based upon the error-corrected read data.Other References
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