U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Multi-bit flash memory device and program method thereof

Patent 7813187 Issued on October 12, 2010. Estimated Expiration Date: Icon_subject November 12, 2027. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Error management processes for flash EEPROM memory arrays
Patent #: 5475693
Issued on: 12/12/1995
Inventor: Christopherson, et al.

Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same
Patent #: 5923587
Issued on: 07/13/1999
Inventor: Choi

Reversibly expandable structures having polygon links
Patent #: 6082056
Issued on: 07/04/2000
Inventor: Hoberman

Data management for multi-bit-per-cell memories
Patent #: 6532556
Issued on: 03/11/2003
Inventor: Wong, et al.

Method and structure for efficient data verification operation for non-volatile memories
Patent #: 6560143
Issued on: 05/06/2003
Inventor: Conley, et al.

Non-volatile semiconductor memory device
Patent #: 6917547
Issued on: 07/12/2005
Inventor: Kanamori, et al.

Flash memory device having multi-level cell and reading and programming method thereof
Patent #: 7035144
Issued on: 04/25/2006
Inventor: Kim, et al.

Multi-level caching in data storage devices Patent #: 7099993
Issued on: 08/29/2006
Inventor: Keeler

Inventor

Assignee

Application

No. 11938603 filed on 11/12/2007

US Classes:

365/189.05Having particular data buffer or latch

Examiners

Primary: Dinh, Son

Attorney, Agent or Firm

Foreign Patent References

  • 1998-027610 KR 07/01/1998
  • 1020060051898 KR 05/01/2006

International Class

G11C 7/00

Abstract

A method for programming a flash memory device including a plurality of memory cells, each storing multi-bit data, includes reading data from selected memory cells. An error of the read data is detected and corrected. Input program data is programmed into the selected memory cells based upon the error-corrected read data.

Other References

  • English Abstract for Publication No. 1020060051898.
  • English Abstract for Publication No. 1998-027610.
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