Method and mechanism for performing timing aware via insertion
Patent 7665052 Issued on February 16, 2010. Estimated Expiration Date: 
November 17, 2026. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 17, 2026. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for identifying gated clocks within a circuit design using a standard optimization tool Method and apparatus for reducing power consumption in an integrated circuit chip Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic Patent #: 7290226 InventorsAssigneeApplicationNo. 11601246 filed on 11/17/2006US Classes:716/6Timing analysis (e.g., delay time, path delay, latch timing)ExaminersPrimary: Siek, VutheAttorney, Agent or FirmInternational ClassG06F 17/50AbstractA method and system to insert redundant vias while preserving timing is disclosed. The system and method preserve the timing during redundant via insertion, which utilizes incremental timing and extraction updates. A budgeting based approach and a path based approach to the method are disclosed. The budgeting approach is faster, while the path based method has a better insight of the worst slack/slew for the entire design.Field of Search716/ 5716/ 6 | |
