Reducing mission signal output delay in IC having mission and test modes
Patent 7649379 Issued on January 19, 2010. Estimated Expiration Date: 
December 26, 2027. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 26, 2027. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesTesting circuit provided in digital logic circuits Probeless testing of pad buffers on wafer Boundary scan device Patent #: 7428676 AbstractAn integrated circuit apparatus includes a switching circuit that provides respective signal paths to permit a mission signal, a test signal, and a boundary scan test signal to share an output terminal. The signal path associated with the mission signal imposes a smaller switching delay than do the signal paths associated with the test and boundary scan test signals.Field of SearchWITH TEST FACILITATING FEATUREMULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.) Having details of setting or programming of interconnections or logic functions Sequential (i.e., finite state machine) or with flip-flop Digital logic testing Programmable logic array (PLA) testing Scan path testing (e.g., level sensitive scan design (LSSD)) Boundary scan | |
