Method of making vertical transistor with horizontal gate layers
July 31, 2026. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesThree dimensional famos memory devices and methods of fabricating Multimedia storage system with highly compact memory device Process for high density split-gate memory cell for flash or EPROM Process for high density flash EPROM cell Three dimensional FAMOS memory devices Reconfigurable programmable interconnect architecture Method of fabricating non-volatile sidewall memory cell Semiconductor device and method of manufacturing the same Very high-density DRAM cell structure and method for fabricating it 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation InventorAssigneeApplicationNo. 11496655 filed on 07/31/2006US Classes:438/259Including forming gate electrode in trench or recess in substrateExaminersPrimary: Pert, EvanAttorney, Agent or FirmForeign Patent References
International ClassH01L 21/336AbstractVertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA. The memory array or the logic array includes densely packed cells, each cell having a semiconductor pillar providing shared source and drain regions for two vertical body transistors that have control gates overlaying floating gates distributed on opposing sides of the semiconductor pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data or to represent a logic function, an area of only 2F2 is needed per respective bit of data or bit of logic, where F is the minimum lithographic feature size.Other References
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