Patent ReferencesPacket header generation and detection circuitry DQPSK mapping circuit Recovery and transmission of return-to-zero formatted data using non-return-to-zero devices Clock recovery circuit with second order digital filter Patent #: 7127017 InventorsAssigneeApplicationNo. 11649086 filed on 01/03/2007US Classes:455/557Interface attached device (e.g., interface with modem, facsimile, computer, etc.) , 375/206ExaminersPrimary: Dao, Minh DAttorney, Agent or FirmInternational ClassH04B 1/38AbstractA transmit digital processing system for wireless transmission of HDMI and/or DVI data using an FPGA. The FPGA converts the data into two data streams and includes a front end component multiplexing video data with control data. A complementary receive FPGA is also disclosed. | |