Equivalent gate count yield estimation for integrated circuit devices

Patent 7477961 Issued on January 13, 2009. Estimated Expiration Date:

May 12, 2026. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Assignee

international Business Machines Corporation

Application

No. 11382963 filed on 05/12/2006

US Classes:

700/121Integrated circuit production or semiconductor fabrication

Examiners

Primary: Jarrett, Ryan A.
Assistant: Rapp, Chad

Attorney, Agent or Firm

International Class

G06F 19/00

Abstract

A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

Other References

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