Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module
June 26, 2027. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAmplifier and method for sensing having a pre-bias or coupling step Reading circuit for memory cell devices having a low supply voltage Current-mode sense amplifier Low power, single-phase latch-type current sense amplifier Current sensing amplifier Equipotential sense methods for resistive cross point memory cell arrays Interconnection network for connecting memory cells to sense amplifiers Memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and method for fabricating it Methods and structure for maximizing signal to noise ratio in resistive array Reading circuit for a non-volatile memory InventorsAssigneeApplicationNo. 11768508 filed on 06/26/2007US Classes:365/209, Magnetic365/210, Reference or dummy element365/158, Magnetoresistive327/53Current mirrorExaminersPrimary: Phan, TrongAttorney, Agent or FirmForeign Patent References
International ClassesG11C 7/02G11C 11/00 AbstractAn integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.Other References
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