Synchronous semiconductor memory device having on-die termination circuit and on-die termination method
May 23, 2027. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHigh-speed bus structure for printed circuit boards On-chip termination Apparatus and method for dynamic on-die termination in an open-drain bus architecture system On-chip termination circuit Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation Circuit and method for interfacing to a bus channel Method of addressing individual memory devices on a memory module Patent #: 6832177 InventorsAssigneeApplicationNo. 11802443 filed on 05/23/2007US Classes:365/189.05, Having particular data buffer or latch365/194, Delay365/233, Sync/clocking326/30Bus or line termination (e.g., clamping, impedance matching, etc.)ExaminersPrimary: Ho, HoaiAttorney, Agent or FirmInternational ClassG11C 7/00AbstractA synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation. | |
