Parallel switching architecture for multiple input/output
Patent 7397808 Issued on July 8, 2008. Estimated Expiration Date: 
June 9, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 9, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMemory management unit architecture for switch fabric Patent #: 7136381 InventorsAssigneeApplicationNo. 10457225 filed on 06/09/2003US Classes:370/413, Having both input and output queuing370/386, Particular switching network arrangement370/411, Including sorting and merging networks370/412, Queuing arrangement370/419Input or output circuit, per se (i.e., line interface)ExaminersPrimary: Vu, Huy D.Assistant: Rivas, Salvador E. Attorney, Agent or FirmForeign Patent References
International ClassH04L 12/56AbstractA multiple input/output-queued(MIOQ) switch is presented. This MIOQ switch comprises a (k,m)-dimensional crossbar fabric having k ingress lines and m egress lines; N input buffers at each input; M output buffers at each output; N×k interconnection networks each of which is able to move a packet from each input to one of the k egress lines; and m×M interconnection networks each of which is able to move the arrived packet at output from the m egress lines to one of the M(wherein M is m or N) output buffers. The multiple input/output-queued(MIOQ) switch according to the present invention requires no “speed-up”. Performance matches the performance of an output-queued switch.Other References
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