Self-healing chip-to-chip interface
January 9, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAzimuth processor for SAR system having plurality of interconnected processing modules Semiconductor memory having redundancy circuit for relieving defects Optical transmission apparatus Clocked logic circuitry preventing double driving on shared data bus Fault tolerant data exchange unit Asynchronous transfer mode link recovery mechanism Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system Fault-tolerant hierarchical bus system and method of operating same Method for changing-over to standby for a transmission device for the bidirectional transmission of digital signals and arrangement for carrying out the method Method and apparatus for error compensation using a non-linear digital-to-analog converter InventorsAssigneeApplicationNo. 10339757 filed on 01/09/2003US Classes:370/217, Bypass an inoperative switch or inoperative element of a switching system710/305, Bus interface architecture342/25E, With time domain processing of the SAR signals in azimuth, e.g. time focusing (EPO)365/200, Bad bit385/24, Plural (e.g., data bus)370/462, Arbitration for access to a channel714/45, Output recording (e.g., signature or trace)370/218, Packet switching system or element710/316, Path selecting switch714/1, Reliability and availability370/220, Standby switch341/138, Nonlinear714/726, Scan path testing (e.g., level sensitive scan design (LSSD))370/399, Employing logical addressing for routing (e.g., VP or VC)714/738, Including test pattern generator326/10, Redundant370/225, Bypass an inoperative channel365/201, Testing326/41, Significant integrated structure, layout, or layout interconnections365/189.02, Multiplexing257/48, TEST OR CALIBRATION STRUCTURE714/25, Fault locating (i.e., diagnosis or testing)345/98Specific display element control means (e.g., latches, memories, logic)ExaminersPrimary: Orgad, EdanAssistant: Ahmed, Salman Attorney, Agent or FirmForeign Patent References
International ClassG01R 31/08AbstractA method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.Other References
Field of SearchBypass an inoperative channel | |
