Iso/nested control for soft mask processing

Patent 7328418 Issued on February 5, 2008. Estimated Expiration Date:

February 1, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Full Text

Patent References

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Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching
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Patent #: 7008866
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Iso/nested cascading trim control with model feedback updates Patent #: 7209798
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Inventors

Assignee

Tokyo Electron Limited

Application

No. 11046903 filed on 02/01/2005

US Classes:

716/10, Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)716/1, CIRCUIT DESIGN716/19, DESIGN OF SEMICONDUCTOR MASK216/51, Mask resist contains inorganic material430/316, Multiple etching of substrate438/723, Silicon oxide or glass438/585, Insulated gate formation700/121Integrated circuit production or semiconductor fabrication

Examiners

Primary: Chiang, Jack
Assistant: Doan, Nghia M.

International Classes

G06F 17/50
G06F 9/45

Abstract

This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.

Other References

Masatoshi Nagase et al., “Advanced Gate Etching for Accurate CD Control for 130-nm Node ASIC Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, vol. 17 (No. 3), pp. 281-285, (Aug. 2004).
Wesley C. Natzle et al., “Trimming of Hard-masks by Gaseous Chemical Oxide Removal (COR) for Sub-10nm Gates/Fins, for Gate Length Control and for Embedded Logic,” ASMC '04 IEEE Conference and Workshop, pp. 61-65, (May 4-6, 2004).
Mitsugu Tajima et al., “Advanced process control for 40nm Gate fabrication,” Conf. Proc., 2003 IEEE Int'l Symp. Semiconductor Manufacturing, pp. 115-118, (Sep. 30, 2003).