Method and system for configuring an integrated circuit

Patent 7314174 Issued on January 1, 2008. Estimated Expiration Date:

October 22, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Programmable address decoder for programmable logic device
Patent #: 5821772
Issued on: 10/13/1998
Inventor: Ong, et al.

Field programmable gate array having programming instructions in the configuration bitstream
Patent #: 5892961
Issued on: 04/06/1999
Inventor: Trimberger

Computational field programmable architecture
Patent #: 6140839
Issued on: 10/31/2000
Inventor: Kaviani, et al.

Method and structure for configuring FPGAS
Patent #: 6204687
Issued on: 03/20/2001
Inventor: Schultz, et al.

Configuration bus interface circuit for FPGAs
Patent #: 6429682
Issued on: 08/06/2002
Inventor: Schultz, et al.

Supporting multiple FPGA configuration modes using dedicated on-chip processor
Patent #: 6496971
Issued on: 12/17/2002
Inventor: Lesea, et al.

Programmable logic device with flexible memory allocation and routing Patent #: 7088134
Issued on: 08/08/2006
Inventor: Agrawal, et al.

Inventors

Assignee

Xilinx , Inc.

Application

No. 10970964 filed on 10/22/2004

US Classes:

235/462.1, Means to decode a 2-D bar code235/462.09, 2-D bar code235/462.01, Bar code326/38, Having details of setting or programming of interconnections or logic functions712/10, Array processor326/39, Array (e.g., PLA, PAL, PLD, etc.)716/16, PLA, PLD, FPGA, OR MCM326/41Significant integrated structure, layout, or layout interconnections

Examiners

Primary: Le, Thien M.
Assistant: Labaze, Edwyn

Attorney, Agent or Firm

Kanzaki; Kim

International Classes

G06K 7/10
G06K 9/36
G06K 9/80

Abstract

A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.

Other References

Xilinx, Inc.; Application Note: Virtex Series; XAPP151 (v1.7); “Virtex Series Configuration Architecture User Guide”, Oct. 20, 2004; available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124; pp. 1-45.
U.S. Appl. No. 10/971,394, filed Oct. 22, 2004, Vadi et al.
U.S. Appl. No. 10/836,722, filed Apr. 30, 2004, Vadi et al.
U.S. Appl. No. 10/796,750, filed Mar. 8, 2004, Vadi et al.
U.S. Appl. No. 10/377,857, filed Feb. 28, 2003, Blodget et al.