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Systems, methods, and media for block-based assertion generation, qualification and analysis

Patent 7313772 Issued on December 25, 2007. Estimated Expiration Date: Icon_subject May 24, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

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Inventors

Assignee

Application

No. 11136256 filed on 05/24/2005

US Classes:

716/5, Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)716/2, Optimization (e.g., redundancy, compaction)716/9, Detailed placement (i.e., iterative improvement)716/18, Logical circuit synthesizer707/102Generating database or data structure (e.g., via user interface)

Examiners

Primary: Do, Thuan

Attorney, Agent or Firm

Foreign Patent References

  • WO 03/100704 WO 12/01/2003

International Class

G06F 17/50

Abstract

Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session preferences including a selection of one or more assertion schemas for use in generating the assertions, where the selected assertion schema each have one or more design attributes. The embodiment may also include parsing the design to determine locations in the design for the assertions based on the design architecture, structure, and hierarchy and generating the assertions based on at least the session preferences, the determined locations for the assertions, and the design attributes associated with the selected assertion schema. Generating the assertions may further include analyzing and modifying existing assertions based on the session preferences and design attributes or qualifying the assertions for consistency and compliance with the session preferences and design attributes.

Other References

  • Research Disclosure, “A Method to Optimize Environment Models in Format Verification,” International Business Machines Corporation, Apr. 1999, pp. 537-538.
  • Research Disclosure, “An Iterative Method to Reduce State Space for Efficient Formal Verification,” International Business Machines Corporation, Mar. 1998, p. 291.
  • Research Disclosure, “Large Pages Using Power PC BATs,” and “A Graphical Interface for Formulating CTL Rules for Model Checking,” International Business Machines Corporation, Jun. 1998. pp. 841-842.
  • Accelerating “Concept to RTL for System-on-Chip Designs,” 2003 Synopsys, Inc., pp. 1-126.
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