Microcomputer with code conversion
Data-processing apparatus and method
Interface between a microprocessor and a coprocessor
Method and apparatus for collecting execution status data of structured program
Integrated circuit microprocessor with programmable chip select logic
Asynchronous interrupt inhibit method and apparatus for avoiding interrupt of an inseparable operation
Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
ApplicationNo. 10283397 filed on 10/29/2002
US Classes:712/203, Multiprocessor instruction712/226, Instruction modification based on condition712/234, Conditional branching712/40, External sync or interrupt signal712/209, Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)712/210Decoding instruction to accommodate variable length instruction or operand
ExaminersPrimary: Pan, Daniel H.
Attorney, Agent or Firm
Foreign Patent References
International ClassesG06F 9/312
AbstractAn apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.