Buffer circuit having electrostatic discharge protection
Patent 7271629 Issued on September 18, 2007. Estimated Expiration Date: 
November 15, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 15, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesElectrostatic discharge protection circuit Integrated circuit I/O buffer with series P-channel and floating well Electrostatic discharge circuit ESD-protection device with active R-C coupling to gate of large output transistor Patent #: 6552583 InventorsAssigneeApplicationNo. 10986771 filed on 11/15/2004US Classes:327/112, Push-pull327/437, Complementary metal-oxide semiconductor (CMOS)327/576, Complementary transistors361/56, Voltage responsive326/86, Bus driving439/248Connector including housing or panel to support holderExaminersPrimary: Tra, QuanAssistant: Englund, Terry L. Attorney, Agent or FirmInternational ClassesH02H 3/22H02H 9/04 AbstractThe buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad. | |
