Speech recognition system
Patent 7266496 Issued on September 4, 2007. Estimated Expiration Date: 
December 24, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 24, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRecognizer for recognizing voice messages in pulse code modulated format Method of training a speaker-dependent speech recognizer with automated supervision of training sufficiency Pattern recognition system and method Wavelet-based energy binning cepstal features for automatic speech recognition Spelling speech recognition apparatus and method for communications combined engine system and method for voice recognition Method and apparatus for constructing voice templates for a speaker-independent voice recognition system Patent #: 6735563 InventorsAssigneeApplicationNo. 10328482 filed on 12/24/2002US Classes:704/241, Dynamic time warping704/201, For storage or transmission704/219, Linear prediction704/231, Recognition704/221, Pattern matching vocoders704/217, Autocorrelation704/251, Word recognition704/243, Creating patterns for matching704/256.8, Discrete density, e.g., Vector Quantization preprocessor, look up tables (EPO)704/257, Natural language704/255Specialized modelsExaminersPrimary: Chawan, VijayInternational ClassG10L 15/08DescriptionBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech recognition system, more particularly to a speech recognition system designed by the application specific integrated circuit (ASIC) architecture and divided into 4 modules by the modular design. 2. Description of the Related Art As the portable system prevails and the application of voice for man-machine interface becomes more important day after day, the implementation of the algorithm of speech processing onto the hardware demands immediate attention. The speechprocessing used by such portable system generally adopts a single chip processor or digital signal processor to accomplish the purpose. The cost of single chip processor is low, but the computing function is not as powerful and difficult to carry outthe more complicated speech computation. If digital signal processor is used for developing the system, it takes shorter time and has more flexibility in design, but the cost is higher. The present invention uses ASIC architecture to fully implementthe whole speech recognition process (from inputting the voice to outputting the recognition result); the speed of execution is faster than that of the digital signal processor, and the cost for such implementation on a portable system is lower than thaton a digital signal processor. SUMMARY OF THE INVENTION The primary objective of the present invention is to use an application specific integrated circuit (ASIC) architecture to design the speech recognition system in order to expedite its execution speed and lower the cost of implementing suchsystem onto the portable system. The secondary objective of the present invention is to use the modular design to divide the speech recognition system into 4 modules; each module forms an intellectual product (IP) component by itself, and each IP component can work with variousproducts and application requirements for the design reuse, and thus greatly shorten the time to market. To accomplish the abovementioned objectives, the present invention provides a speech recognition designed by using the ASIC architecture to input the speech and output the recognition result. In the meantime, the modular design divides thesystem into 4 modules, and such 4 modules can form an intellectual product each by themselves. The 4 modules include: a control module, for receiving an external signal to control the internal circuit, and such external signal further includes twotypes: training button 60 and recognition button 70; an autocorrelation and linear predictive coefficient (LPC) module, comprising an autocorrelation parameter unit and a linear predictive parameter unit, and such two units can separately find theautocorrelation parameter and the linear predictive parameter to convert an input speech data into an output linear predictive parameter; a cepstrum module for receiving the linear predictive coefficient and outputting the cepstrum coefficient as theaudio data module; a dynamic timing warping (DTW) module, using a DTW algorithm to compare the video data model to output the recognition score; additionally, it also comprises a speech receiving module, composed of a set of shift registers and a set ofgeneral registers acting as the external sampling frequency and the internal operating frequency interfaces to convert the received speech data frequency until it is consistent with the operating frequency of the internal circuit first, and then read thecomputation result; additionally, it also comprises an external memory (RAM) for storing the cepstrum of the training speech data; wherein the training button passes through the autocorrelation and linear predictive coefficient module and the cepstrummodule after the system receives the training speech data, and then save the cepstrum of the training speech data into the RAM; the recognition model passes through the autocorrelation and linear predictive coefficient module and the cepstrum moduleafter the system receives the recognition speech data, and then save the cepstrum of the recognition speech data into the internal register and then informs the recognition button to start accessing the cepstrum of the training speech data previouslysaved in the RAM and the cepstrum of the recognition speech data of the internal register for performing the recognition and further outputting the recognition score. After each record of training speech data obtains the recognition score, the controlmodule will take over to select the best score to output the recognition result. To make it easier for our examiner to understand the objective of the invention, its structure, innovative features, and performance, we use a preferred embodiment together with the attached drawings for the detailed description of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of the structure of the present invention. FIG. 2 is a detailed block diagram of the structure of the present invention. FIG. 3 is a diagram of the structure of the circuit of the speech receiving module of the present invention. FIG. 4 is a circuit diagram of the structure of decision logic of the present invention. FIG. 5 is a circuit diagram of the structure of the linear predictive coefficient unit of the present invention. FIG. 6 is a circuit diagram of the structure of the linear predictive unit of the present invention. FIG. 7 is a circuit diagram of the structure of the cepstrum module of the present invention. FIG. 8 is an illustrative diagram of the input/output (I/O) interface of the processing element of the present invention. FIG. 9 is an illustrative diagram of the interior of the processing element of the present invention. FIG. 10 is an illustrative diagram of the 100×100 lattice of the dynamic timing warping of the present invention. FIG. 11 is an illustrative diagram of the lattice of the dynamic timing warping of the present invention after dividing the score. FIG. 12 is a diagram of the data path of the recognition module of the present invention. Table 1 shows the timing control of the front section of FIG. 11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS To disclose the present invention, preferred embodiments accompanied with diagrams are described as follows. The speech recognition system of the present invention, starting from inputting the speech data into the microphone, requires thefollowing processes: Low Pass Filter 1, a Pre-emphasis 2, Windowing 3, Autocorrelation Analysis 4, Endpoint Detection 5, Linear Predictive Coefficient Analysis (LPC Analysis) 6, Cepstrum Extraction 7, Reference Updating 8, Dynamic Timing Warping (DTW) 9,and Decision Logic 10. At last, the recognition result is displayed (from the 7-sectional display or LED display). The whole speech recognition system is implemented by the application specific integrated circuit (ASIC) architecture. FIG. 1. is theillustrative diagram of the structure of the present invention, wherein the input is Speech 80, and the output is the Recognition Result 90. In the meantime, the modular design divides the speech recognition system of the present invention into 4modules for its design. Each of the four modules can form an intellectual product (IP) component on its own, and each IP component can work with various products and application requirements for the design reuse to greatly shorten the time to market. The 4 modules include: a Control Module 10 for receiving external signals and controlling the internal circuit, and the external signals include two types: a Training Button 60 and a Recognition Button 70; an Autocorrelation & LPC Module 20 is composedof autocorrelation coefficient unit and linear predictive coefficient unit, and such two units can separately find the autocorrelation coefficient and linear predictive coefficient by converting the speech data into the linear predictive parameter; aCepstrum Module 30 for receiving the foregoing linear predictive coefficient and outputting the cepstrum as the speech data model; a Dynamic Timing Warping (DTW) algorithm; a DTW Module 40, adopting a Dynamic Timing Warping (DTW) algorithm, such that therecognition score is outputted after the foregoing speech module is compared. Additionally, the speech recognition also includes a speech receiving module which is composed by a set of shift registers and a set of regular registers, acting as theinterfaces of the external sampling frequency and internal operating frequency to convert the received speech data frequency until the operating frequency of the internal circuit is consistent, and then reading out the computation result; an externalmemory (RAM) 50 for storing the cepstrum of the speech data. In which, the low pass filter is disposed outside the chip, which is implemented by separate components. The division of operation of the other four modules is described below: The controlmodule 10 processes the reference updating 8 and the decision logic 10; the autocorrelation and linear predictive coefficient modules 20 processes the pre-emphasis 2, windowing 3, autocorrelation analysis 4, endpoint detection 5, and LPC analysis 6. Thecepstrum module 30 processes cepstrum extraction 7. The DTW recognition module 40 processes the dynamic timing warping (DTW) 9. The control module 10 is connected to the autocorrelation and linear predictive coefficient module 20 unidirectionally, that is, signals only flow from the control module 10; and the control module 10 is connected to the capstrum module 30 andDTW module 40 bidirectionally. The autocorrelation and linear predictive coefficient module is connected to the cepstrum module 30 unidirectionally, that is, signals are transferred from the autocorrelation and linear predictive coefficient module tothe cepstrum module 30. When the speech recognition system of the present invention receives different control signals, the system will have different processing modules according to the different control signals. There are two modules as described below: (1) trainingbutton for receiving different training speech data and saving the cepstrum of the training speech data into the external memory RAM 50 after passing through the autocorrelation and linear predictive coefficient module 20 and the cepstrum module 30, and(2) recognition module for receiving the recognition speech data and saving the cepstrum of the recognition speech data in the internal register after passing through the autocorrelation and LPC module 20 and the cepstrum module 30, and informing the DTWrecognition module 40 to start accessing the cepstrum of the training speech data previously stored in the external memory RAM 50 and the cepstrum of the recognition speech data of the internal register for recognition and outputting the recognitionscore. After every record of the training speech data obtains the recognition score, the control module 10 will take over and select the best score to output the recognition score. 90. The detailed structure of the present invention as shown in FIG. 2 will be described as follows: Speech Receiving Module: the whole system includes two frequencies; one is the external sampling frequency, and the other is the internal operating frequency. Since the frequencies of the two are different, we have designed a speech receivingmodule to act as the interface for these two different frequencies. For example, if the external sampling frequency is 8 KHz and the operating frequency of the internal circuit is 10 MHz, then the frequency 8 KHz is used to receive speech data, whilethe frequency 10 MHz is used to read out the computation result. The circuit structure of the speech receiving module is shown in FIG. 3. Control Module: The control module 10 is divided into two main parts; one is the finite status machine (FSM) of the external accessing frequency (for example 8 KHz) and the other one is the internal operating frequency (for example 10 MHz). These two parts are separately controlled by the external signals to control the internal circuit. The finite status machine of the external sampling frequency mainly controls the speech receiving module. After the collection of speech data iscompleted, the autocorrelation and LPC module 20 is noticed to start reading the speech data for computation. The finite status machine of the internal operating frequency mainly controls the external memory RAM 50 and the access of the internalregister, and coordinates the communication between modules. When the cepstrum module 30 completes issuing the signal, the control memory or register will write the speech parameter according to different operating module. For training button, thespeech parameter is written into the external memory RAM 50. For recognition button, after the speech parameter is written into the internal register, the DTW recognition module 40 is noticed to perform the comparison. When the DTW recognition module40 outputs every record of recognition score, and then notices the decision logic to perform the computation, and finally outputs the recognition result 90. The decision logic will output the every recognition score outputted from the DTW recognitionmodule 40 for determining the best score. FIG. 4 shows circuit of the decision logic, and the decision logic is mainly composed of the minimum selection circuit and a counter. When the start signal is initialized, and then the recognition score isinputted. The present smallest recognition score is used as the minimum selection. If the outputted recognition score is smaller than the present smallest recognition score, then write the inputted recognition score into Register A, and the reading ofthe counter into Register B, and such counter is controlled by the start signal. After all recognition scores are inputted, then the value in Register B is the recognition result. Autocorrelation and LPC Module: The autocorrelation and LPC module 20 is divided into 2 main units: autocorrelation unit and the linear predictive coefficient unit for respectively find the autocorrelation coefficient and the linear predictivecoefficient. The autocorrelation unit receives 256 records of speech data, and output 11 scale-ten parameters. The autocorrelation unit is divided into 3 main sections: pre-emphasis section, Hamming window section, and autocorrelation section. Afterunderstanding the concepts of these three sections, the present invention designs the circuit with the autocorrelation unit as shown in FIG. 5. In the figure, two multipliers are used; the multiplier at the top is used to multiply the speech data withthe Hamming window, and the value of the Hamming window will be saved in the Hamming ROM. The multiplier below is combined with an adder to form a set of multiplication accumulation circuit to find the 11 scale-ten autocorrelation coefficients insequence. The linear predictive unit is used to find the linear predictive coefficient, and its computation includes three main sections: accumulation, division, and reference updating, and the structure of its circuit is shown in FIG. 6. The Registers A1to A10 on the left are used to individually store the autocorrelation coefficients, and the 19 shift registers on the right are used to save the linear predictive coefficients. The Register Sum below is used for accumulation, and the Register E is usedto store the estimated errors. Cepstrum Module: The cepstrum module 30 receives the linear predictive coefficient and output the cepstrum parameter. Furthermore, under the consideration of area, its circuit shown in FIG. 7 only uses a set of multiplier and adder, a set of ten16-bit LPC RAMs to save the linear predictive coefficients, a 16-bit constant ROM to save 45 constants. Ten 16-bit Cep RAMs are used to store the cepstrum parameters. DTW Recognition Module: The DTW recognition module 40 adopts the Dynamic Timing Warping (DTW) algorithm, therefore the key point of designing the recognition unit relies on two sections: Processing Element (PE) design and control method. What the processing element needs to do is to select the minimum accumulation value for the distances in three directions, and calculate the distance value of this element, and add the accumulation value of the distance outputted up to thiselement. FIG. 8 is the illustrative diagram of the input/output (I/O) interface of the processing element. The tmp(i-1,j), tmp(i-1,j-1), tmp(i,j-1) are the distances in three directions, and the vectors of the distance value of the cepstrum parametersof Uj and Ri are the, distance values of this processing element, and select the minimum accumulation value among the distances in three directions, and add the outputted distance value of this processing element as tmp(i,j). FIG. 9 is the illustrativediagram of the interior of the processing element, and the tmp(i-1,j), tmp(i-1,j-1), tmp(i,j-1) are the distances in three directions. Through the minimum selector in the figure, the minimum is selected from the accumulation value of the distances inthe three directions. Uj and Ri input the value of the vector of the cepstrum parameter into the counter, and output the distance value of this processing element and the output of the minimum selector as well as inputting into the adder. The adderwill output the tmp(i,j). Then we will introduce the actual circuit of the 100×100 dynamic timing warping. FIG. 10 is the illustrative diagram of lattice. There is a formula: if F is the number of sound frames and W is the warping factor, then the number ofprocessing elements requiring calculation is PEs-F(2W 1)-W(W 1). Therefore in 100×100, and the warping factor is assumed as 15, it takes 2860 times of calculation for the processing elements, which is a very large number. Therefore, in thecontrol circuit, it is appropriate to further introduce the regular control circuit. Firstly, the 2860 processing elements are cut into the front section (0~135), the middle section (136~2754) and the rear section (2755~2859) as shownin FIG. 11. If the timing at each point of the front section needs to be calculated, the timing for the accumulated value of the distances in the three directions will be listed as shown in Table 1. Table 1 shows the timing of each point that requiresusing the distance accumulation value in either the left, lower left, or downward directions and such accumulated value has to be obtained from which one of the shift registers. It is known from Table 1 that the front section is divided into 16 groups;the n group has n points. In these n points, the first point only needs the accumulation value of the distance in the downward direction, and uses the value in the n-1th shift register. The nth point only needs the accumulated distance valuein the left direction and uses the value in the nth shift register. The rest accumulated distance values in the left direction uses the value in the nth register, and the accumulated distance value in the lower left direction uses the value inthe 2(n-1)th shift register, and the accumulated distance value in the downward direction uses the value in the n-1th shift register. The middle section and the rear section may also adopt similar methods to find its rules. FIG. 12 shows the data path of the DTW recognition module. On the upper left corner of the figure, there is a subtraction absolute value accumulated circuit, because it is used for the computation of absolute value of the subtraction for thescale-ten cepstrum parameter, the subtracter is used to find the distance value of this point, and the adder is used to add the accumulated distance value to the distance value of this point. At the bottom of the figure, there is a shift register using31 shift register of the size of register to store the past accumulated distance values. The upper right corner of the figure, there is the minimum circuit among the three accumulated distance values in the left, lower left and downward directions,which uses 3 multiplexers to select the desired value from the shift registers, and through the minimum selector to select the minimum from the accumulated distance values in three directions. While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similararrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. * * * * * |
