Method and apparatus for reducing power consumption in an integrated circuit chip
Patent 7257782 Issued on August 14, 2007. Estimated Expiration Date: 
July 14, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 14, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesTiming driven placement Method and system for creating, validating, and scaling structural description of electronic device Patent #: 6216252 InventorsAssigneeApplicationNo. 11182100 filed on 07/14/2005US Classes:716/2, Optimization (e.g., redundancy, compaction)716/6, Timing analysis (e.g., delay time, path delay, latch timing)716/9, Detailed placement (i.e., iterative improvement)716/12, Routing (e.g., routing map, netlisting)716/18, Logical circuit synthesizer716/10, Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)716/1CIRCUIT DESIGNExaminersPrimary: Do, ThuanAttorney, Agent or FirmInternational ClassG06F 17/50AbstractA system that reduces power consumption in an integrated circuit. During operation the system receives a placement for the integrated circuit. The system then groups registers in the placement into clusters and builds a temporary clock tree for the registers within the placement. Next the system assigns net weights to clock wires in the temporary clock tree and signal wires between the rest of the cells of the circuit, and uses the assigned net weights to optimize placement of the cells of the circuit by minimizing a sum of the weighted costs of the wires, wherein the weighted cost of a wire is a product of the net weight of the wire and the length of the wire. | |
