Patent ReferencesDual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache Content-based, transparent sharing of memory units Provision of a victim cache within a storage cache hierarchy Multi-level cache system with simplified miss/replacement control On-disk file format for a serverless distributed file system System, method and apparatus for controlling supply of backup power to first and second power planes in the event of a power failure of a main power supply Root complex connection system Data storage cache system shutdown scheme Cache memory eviction policy for combining write transactions Large high bandwidth memory system Patent #: 7089379 InventorAssigneeApplicationNo. 11026736 filed on 12/30/2004US Classes:711/113, Caching711/119, Multiple caches711/122, Hierarchical caches711/133, Entry replacement strategy711/134, Combined replacement modes711/139, No-cache flags711/118, Caching711/6, Virtual machine memory addressing713/171, Having key exchange713/324, By shutdown of only part of system710/314, Common protocol (e.g., PCI to PCI)714/15, State recovery (i.e., process or data file)711/154, Control technique711/162, Backup707/100, DATABASE SCHEMA OR DATA STRUCTURE439/61Receives plural panel circuit edgesExaminersPrimary: Verbrugge, KevinAttorney, Agent or FirmInternational ClassesG06F 12/00G06F 12/08 AbstractApparatus, methods, and program products for storing data address a first cache and a second cache. The second cache is capable of operating in a first mode wherein data read for storage in the first cache is also stored in the second cache, and is capable of operating in a second mode wherein the data stored in the second cache does not include at least some of the data read for storage in the first cache. The data stored in the second cache includes data that has been removed from the first cache. Thus the contents of the second cache are at least partially exclusive of the contents of the first cache. The described apparatus, methods, and program products are advantageously employed in multi-level caching systems wherein the caches may be approximately the same size. | |