Estimation circuit for time-interleaved ADC and method thereof

Patent 7253762 Issued on August 7, 2007. Estimated Expiration Date:

April 12, 2026. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Assignee

Realtek Semiconductor Corp.

Application

No. 11279556 filed on 04/12/2006

US Classes:

341/155, Analog to digital conversion341/120, CONVERTER CALIBRATION OR TESTING341/118CONVERTER COMPENSATION

Examiners

Primary: Williams, Howard L.

Attorney, Agent or Firm

Hsu; Winston

Foreign Patent References

2000059219 JP 02/01/2000
00456108 TW 09/01/2001

International Class

H03M 1/12

Abstract

The present invention provides an apparatus and a method for estimating at least one of timing, gain, and offset errors of a time-interleaved ADC. The apparatus has a first ADC, a second ADC, a converter, an estimator, and a compensator. The converter has a Fourier Transform converter and a calculator.

Other References

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