Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA

Patent 7249010 Issued on July 24, 2007. Estimated Expiration Date:

April 3, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventor: Burroughs, et al.

Optimization of storage and power consumption with soft error predictor-corrector
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Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays Patent #: 7036059
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Inventors

Assignee

Xilinx , Inc.

Application

No. 10407280 filed on 04/03/2003

US Classes:

703/21, Computer or peripheral device702/58, For electrical fault detection702/59, Fault location702/185, Cause or fault identification716/16, PLA, PLD, FPGA, OR MCM324/751, Using electron beam probe714/10, Of processor714/725Programmable logic array (PLA) testing

Examiners

Primary: Shah, Kamini
Assistant: Lo, Suzanne

Attorney, Agent or Firm

Cartier; Lois D.

International Classes

G06F 9/44
G06F 13/10
G06F 13/12
G06F 13/00
G06F 17/50
G06F 9/00
G01R 31/08
G01F 19/00
G06F 11/34
G06F 15/00
G21C 17/00
H03K 17/693
H03K 17/687

Abstract

Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.

Other References

Hang T. Nguyen, “A Systematic Approach to Processor SER Estimation and Solutions”, Oct. 6, 2002, Intel Corp., 26 pgs.
Carmichael et al. “Correcting Single-Event Upsets Through Virtex Partial Configuration”, Jun. 1, 2000, Xilinx, Inc. 12 pgs.
Meggyesi et al., “FPGA Design in the Presence of Single Event Upsets”, Oct. 1, 1999, 4 pgs.
A.M. Finn, “System Effects of Single Event Upsets”, Computers in Aerospace VII Conference, Oct. 3-5, 1999, AIAA, pp. 994-1002.
Wirthlin et al. “The Effects of Upsets within the Configuration Memory of SRAM FPGAs” 2002, 21 pgs.
Eric Johnson et al.; “Single-Event Upset Simulation on an FPGA”; LA-UR-02-2907; Engineering of Reconfigurable Systems and Algorithms (ERSA); Jun. 24-27, 2002; 6 pages.