Patent ReferencesPartitioning the processors of a massively parallel single array processor into sub-arrays selectively controlled by host computers Method and apparatus for integrated local and express routing in a multiprocessor Scalable switching network Distributed computing system using virtual buses and data communication method for the same Patent #: 6680915 InventorsAssigneeApplicationNo. 11110344 filed on 04/19/2005US Classes:712/28, Distributed processing system709/238, COMPUTER-TO-COMPUTER DATA ROUTING712/13, Partitioning709/243, Decentralized controlling370/422, Centralized switching370/254, NETWORK CONFIGURATION DETERMINATION370/388, Multistage switch716/17Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)ExaminersPrimary: Kim, Kenneth S.Attorney, Agent or FirmInternational ClassG06F 15/163AbstractA multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.Other References
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