U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition

Patent 7246217 Issued on July 17, 2007. Estimated Expiration Date: Icon_subject April 19, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Partitioning the processors of a massively parallel single array processor into sub-arrays selectively controlled by host computers
Patent #: 5175865
Issued on: 12/29/1992
Inventor: Hillis

Method and apparatus for integrated local and express routing in a multiprocessor
Patent #: 5546596
Issued on: 08/13/1996
Inventor: Geist

Scalable switching network
Patent #: 5841775
Issued on: 11/24/1998
Inventor: Huang

Distributed computing system using virtual buses and data communication method for the same Patent #: 6680915
Issued on: 01/20/2004
Inventor: Park ,   et al.

Inventors

Assignee

Application

No. 11110344 filed on 04/19/2005

US Classes:

712/28, Distributed processing system709/238, COMPUTER-TO-COMPUTER DATA ROUTING712/13, Partitioning709/243, Decentralized controlling370/422, Centralized switching370/254, NETWORK CONFIGURATION DETERMINATION370/388, Multistage switch716/17Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)

Examiners

Primary: Kim, Kenneth S.

Attorney, Agent or Firm

International Class

G06F 15/163

Abstract

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Other References

  • Ron Brightwell and Lee Ann Fisk, “Scalable Parallel Application Launch on Cplant,”8 pp., Nov. 2001, Sandia National Laboratories, Albuquerque, NM.
  • Ron Brightwell, Lee Ann FISK, David S. Greenberg, Tramm Hudson, Mike Levenhagen, Arthur B. MacCabe, and Rolf Riesen, “Massively parallel computing using components” 29 pp. Parallel Computing 25 (2000) 243-266, Elsevier Science B.V.
  • Kevin Pedretti, Ron Brightwell and Joshua Williams, “Cplant Runtime System Supoprt for Multi-Processor and Heterogeneous Compute Nodes”, 8 pp., IEEE International Conference on Cluster Computer, Jun. 2002.
  • Timothy G. Mattson and Greg Henry, “An Overview of the Intel TFLOPS Supercomputer”, 12 pp., Intel Technology Journal vol. 2, No. 1, 1st Q, 1998.
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