Memory control method and memory control apparatus for pipeline processing
Patent 7222219 Issued on May 22, 2007. Estimated Expiration Date: 
June 8, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 8, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesBranch prediction system for superscalar processor Information processing apparatus having a CPU and an auxiliary arithmetic unit for achieving high-speed operation Decoupled fetch-execute engine with static branch prediction support Patent #: 6523110 InventorAssigneeApplicationNo. 10862345 filed on 06/08/2004US Classes:711/137, Look-ahead711/204, Predicting, look-ahead711/213, Generating prefetch, look-ahead, jump, or predictive address712/239, Branch prediction712/34Including coprocessorExaminersPrimary: Elmore, Reba I.Attorney, Agent or FirmInternational ClassG06F 12/00AbstractA signal generator detects a stage in which a central processing unit (CPU) reads an interrupt vector number from an instruction controller based on an address on an address bus and generates an address of a ROM to which the CPU makes access subsequently. The generated address is defined as a pre-reading address and this pre-reading address is supplied to the ROM via a selector before the CPU starts accessing to the ROM. In this case, an output buffer is turned off. Thereafter, when the CPU starts accessing to the ROM, the selector is switched and the output buffer is simultaneously turned on so that the address on the address bus is supplied to the ROM.Other References
| |
