Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
Patent 7221605 Issued on May 22, 2007. Estimated Expiration Date: August 31, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
365/205, Flip-flop used for sensing365/202, Complementing/balancing365/204, Accelerating charge or discharge365/207, Differential sensing365/189.09, Including reference or bias voltage generator365/149, Capacitors326/17, ACCELERATING SWITCHING365/203, Precharge327/91, Including details of sampling or holding365/210, Reference or dummy element365/190, For complementary information327/52, Differential amplifier365/208, Semiconductors365/185.21, Sensing circuitry (e.g., current mirror)324/765Test of semiconductor device
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.
Other References
U.S. Appl. No. 10/931,786, filed Sep. 1, 2004, Sample and Hold Memory Sense Amplifier.
U.S. Appl. No. 10/931,379, filed Aug. 31, 2004, Capacitively—Coupled Level Restore Circuits for Low Voltage Swing Logic Circuits.
Blalock, Travis N., et al., “A High-speed Sensing Scheme for 1T Dynamic RAMs Utilizing the Clamped Bit-line Sense Amplifier”, IEEE Journal of Solid-State Circuits, 27(4), (Apr. 1992),618-625.
Dhong, Sang H., et al., “High Speed Sensing Scheme for CMIS DRAM's”, IEEE Journal of Solid-State Circuits, vol. 23, No. 1, (Feb. 1998),34-40.
Kuge, Shigehiro , et al., “SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories”, IEEE Journal of Solid-State Circuits, 31(4), (Apr. 1996),pp. 586-591.
Lu, Nicky C., et al., “Half-Vdd Bit-Line Sensing Scheme in CMOS DRAM's”, Journal of Solid-State Circuits, vol. SC-19, No. 4, (Aug. 1984),451-454.
Parke, Stephen A., “Optimization of DRAM Sense Amplifiers for the Gigabit Era”, IEEE, Proceedings of the 40th Midwest Symposium on Circuits and Systems, Sacramento, CA,(1997),pp. 209-212.
Rabaey, Jan M., Digital Integrated Circuits: A Design Perspective, Section 10.4.2, Prentice Hall Electronics and VLSI Series,(1996),596-603.
Suh, Jung-Won , et al., “Offset-Trimming Bit-Line Sensing Scheme for Gigabit-Scale DRAM's”, IEEE Journal of Solid-State Circuits, 31 (7), (Jul. 1996),pp. 1025-1028.
Suma, Katsuhiro , et al., “An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology”, IEEE Journal of Solid-State Circuits, 29(11), (Nov. 1994),pp. 1323-1329.
U.S. Appl. No. 11/493,961, filed Jul. 27, 2006, Switched Capacitor Dram Sense Amplifier with Immunity to Mismatch and Offsets.
U.S. Appl. No. 11/493,960, filed Jul. 27, 2006, Switched Capacitor Dram Sense Amplifier with Immunity to Mismatch and Offsets.
U.S. Appl. No. 11/485,218, filed Jul. 12, 2006, Sample and Hold Memory Sense Amplifier.
U.S. Appl. No. 11/493,113, filed Jul. 26, 2006, Capacitively—Coupled Level Restore Circuits for Low Voltage Swing Logic Circuits.
August 31, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
