Method and apparatus for integrating large and small lot electronic device fabrication facilities
Patent 7218983 Issued on May 15, 2007. Estimated Expiration Date: November 4, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
In at least one aspect, the invention provides an electronic device fabrication facility (Fab) that uses small lot carriers that may be transparently integrated into an existing Fab that uses large lot carriers. A manufacturing execution system (MES) may interact with the inventive small lot Fab as if the small lot Fab is any other Fab component in an existing large lot Fab without requiring knowledge of how to control small lot Fab components (e.g., beyond specifying a processing recipe). A small lot Fab according to the present invention may encapsulate the small lot Fab's internal use of small lot components and present itself to a large lot Fab's MES as if the small lot Fab is a component that uses large lot carriers.
Przewlocki, H. et al., “Diastemos-computerized system of IC manufacturing control and diagnostics”, 1990, Elektronika, vol. 31 No. 11-12, pp. 38-40, Polish Language. (Abstract only).
Lovell, A. M. et al., “Cell automation: integrating manufacturing with robotics”, Dec. 1990, Solid State Technology, vol. 33 No. 12, p. 37-9.
Prasad, K., “A generic computer simulation model to characterize photolithography manufacturing area in an IC FAB facility”, Sep. 1991, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 14 No. 3, p. 483-7.
Ehteshami, B. et al., “Trade-offs in cycle time management: hot lots”, May 1992, IEEE Transactions on Semiconductor Manufacturing, vol. 5 No. 2, p. 101-6.
Lou, S. et al., “Using simulation to test the robustness of various existing production control policies”, 1991, 1991 Winter Simulation Conference Proceedings, IEEE, p. 261-9.
Berg, R. et al., “The formula: world class manufacturing for hybrid thin-film component production”, 1992, IEEE/SEMI International Semiconductor Manufacturing Science Symposium, pp. 53-60.
Naguib, H., “The implementation of total quality management in a semiconductor manufacturing operation”, 1992, IEEE/SEMI International Semiconductor Manufacturing Science Symposium, p. 63-7.
Rose, D., “Productivity enhancement”, 1992, IEEE/SEMI International Semiconductor Manufacturing Science Symposium, p. 68.
Narayanan, S. et al., “Object-oriented simulation to support operator decision making in semiconductor manufacturing”, 1992, 1992 IEEE International Conference on Systems, Man and Cybernetics, vol. 2, p. 1510-15.
Leonovich, G. A. et al., “Integrated cost and productivity learning in CMOS semiconductor manufacturing”, Jan.-Mar. 1995, IBM Journal of Research and Development, vol. 39 No. 1-2, p. 201-13.
Leonovich, G., “An approach for optimizing WIP/cycle time/output in a semiconductor fabricator”, 1994, Sixteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. ‘Low-Cost Manufacturing Technologies for Tomorrow's Global Economy’. Proceedings 1994 IEMT Symposium, vol. 1, p. 108-11.
Schomig, A. K. et al., “Performance modelling of pull manufacturing systems with batch servers”, 1995, Proceedings 1995 INRIA/IEEE Symposium on Emerging Technologies and Factory Automation. ETFA'95, vol. 3, p. 175-83.
Juba, R. C. et al., “Production improvements using a forward scheduler”, 1996, Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium ‘Manufacturing Technologies - Present and Future’, p. 205-9.
Fuller, L. F. et al., “Improving manufacturing performance at the Rochester Institute of Technology integrated circuit factory”, 1995, IEEE/SEMI 1995 Advanced Semiconductor Manufacturing Conference and Workshop. Theme - Semiconductor Manufacturing: Economic Solutions for the 21st Century. ASMC '95 Proceedings, p. 350-5.
Houmin, Yan et al., “Testing the robustness of two-boundary control policies in semiconductor manufacturing”, May 1996, IEEE Transactions on Semiconductor Manufacturing, vol. 9 no. 2, p. 285-8.
Lopez, M. J. et al., “Performance models of systems of multiple cluster tools”, 1996, Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. Proceedings 1996 IEMT Symposium, pp. 57-65.
Collins, D. W. et al., “Implementation of Minimum Inventory Variability Scheduling 1-Step Ahead Policy(R) in a large semiconductor manufacturing facility”, 1997, 1997 IEEE 6th International Conference on Emerging Technologies and Factory Automation Proceedings, pp. 497-504.
Labanowski, L., “Improving overall fabricator performance using the continuous improvement methodology”, 1997, 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. Theme - The Quest for Semiconductor Manufacturing Excellence: Leading the Charge into the 21st Century. ASMC Proceedings, p. 405-9.
Dudde, R. et al., “Flexible data registration and automation in semiconductor production”, 1997, Proceedings of the SPIE - The International Society for Optical Engineering, p. 171-81.
Padillo, J. M. et al., “A strategic domain: IE in the semiconductor industry”, Mar. 1998, IIE Solutions, pp. 36-40, 42.
Collins, D. W. et al., “Investigation of minimum inventory variability scheduling policies in a large semiconductor manufacturing facility”, 1997, Proceedings of the 1997 American Control Conference, vol. 3, p. 1924-8.
Rose, O., “WIP evolution of a semiconductor factory after a bottleneck workcenter breakdown”, 1998, 1998 Winter Simulation Conference. Proceedings, vol. 2, pp. 997-1003.
Iriuchijima, K. et al., “WIP allocation planning for semiconductor factories”, 1998, Proceedings of the 37th IEEE Conference on Decision and control, vol. 3, p. 2716-21.
Weiss, M., “New twists on 300 mm fab design and layout”, Jul. 1999, Semiconductor International, vol. 22 No. 8, pp. 103-4, 106, 108.
Van Antwerp, K. et al., “Improving work-in-progress visibility with active product tags YASIC manufacture”, Oct. 1999, Micro, vol. 17 No. 9, pp. 67-9, 72-3.
Martin, D. P., “Total operational efficiency (TOE): the determination of two capacity and cycle time components and their relationship to productivity improvements in a semiconductor manufacturing line”, 1999, 10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings, pp. 37-41.
Martin, D. P., “Capacity and cycle time-throughput understanding system (CAC-TUS) an analysis tool to determine the components of capacity and cycle time in a semiconductor manufacturing line”, 1999, 10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings, p. 127-31.
Marcoux, P. et al., “Determining capacity loss from operational and technical deployment practices in a semiconductor manufacturing line”, 1999, 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, pp. 3-5.
Chen, J. C. et al., “Capacity planning for a twin fab”, 1999, 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, p. 317-20.
Wei Jun-Hu et al., “Optimization methodology in simulation-based scheduling for semiconductor manufacturing”, Oct. 2000, Information and Control, vol. 29 No. 5, p. 425-30, Chinese language. (Abstract only).
Hughlett, E., “Incremental levels of automation in the compound semiconductor fab”, Aug. 2001, Compound Semiconductor, vol. 7 No. 7, pp. 69-73.
Sarin, S. C. et al., “Reduction of average cycle time at a wafer fabrication facility”, 2001, 2001 GaAs MANTECH Conference. Digest of Papers, p. 241-6.
Saito, K. et al., “A simulation study on periodical priority dispatching of WIP for product-mix fabrication”, 2002, 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002, p. 33-7.
Wang, J. et al., “The improvement of automated material handling system traffic control”, 2002, 2002 Semiconductor Manufacturing Technology Workshop, p. 271-4.
Wei Jie Lee, “Optimize WIP scale through simulation approach with WIP, turn-over rate and cycle time regression analysis in semiconductor fabrication”, 2002, 2002 Semiconductor Manufacturing Technology Workshop, pp. 299-301.
Young Hoon Lee et al., “Push-pull production planning of the re-entrant process”, 2003, International Journal of Advanced Manufacturing Technology, vol. 22 No. 11-12, p. 922-31.
Garlid, Scott C., “From philosophy to reality. Interpreting the rules of JIT for IC manufacturing”, 1989, SME Technical Paper (Series) MS. Publ by SME, p. 797.
Anon, “Wafer level automation”, Jan. 1995, European Semiconductor, vol. 17 No. 1, p. 2.
Anon, “Coming of fab-wide automation”, May 1998, European Semiconductor Design Production Assembly, vol. 20 No. 5, pp. 21-22.
Pierce, Neal G. et al., “Dynamic dispatch and graphical monitoring system”, 1999, IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings 1999, pp. 65-68.
Nagesh, Sukhi et al., “Intelligent second-generation MES solutions for 300mm fabs”, 2000, Solid State Technology, vol. 43 No. 6, pp. 133-134, 136, 138.
“300mm single-wafer transport”, Jul. 1999, Solid State Technology - semiconductor manufacturing and wafer fabrication, Semicon West '99 Product Spotlight, p. 5.
“300mm single-wafer handling”, Apr. 2000, Solild State Technology, Product News, , p. 99.
Griessing, Juergen et al., “Assessing the feasibility of a 300-mm test and monitor wafer handeling and logistics system”, Jul. 2000, Micro: The 300-mm Imperative, pp. 1-19.
“The Leading Company in Micro environment”, Jan. 3, 2002, Incam Solutions Company, pp. 1-2.
“Improved wafer isolation and additional flexibility”, Jan. 3, 2002, Incam Solutions Company SWIF technology, pp. 1-2.
“SEMI standards compliance” and “Related SEMI standards”, Jan. 3, 2002, Incam Solutions Related standards, p. 1.