Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit
October 10, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesBist jitter tolerance measurement technique Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method Method and Circuit for testing devices with serial data links Method of testing serial interface Measuring jitter of high-speed data channels Semiconductor integrated circuit having a self-testing function Test system rider board utilized for automated at-speed testing of high serial pin count multiple gigabit per second devices Transmission device, reception device, test circuit, and test method Patent #: 7007212 InventorsAssigneeApplicationNo. 10683195 filed on 10/10/2003US Classes:455/67.11, Having measuring, testing, or monitoring of system or part455/67.14, Using a test signal455/66.1, Having diverse art device375/224, TESTING375/226, Phase error or phase jitter375/221, Loopback mode714/724, Digital logic testing714/716, Loop-back714/738, Including test pattern generator702/69, Signal quality (e.g., timing jitter, distortion, signal-to-noise ratio)702/119, Including program initialization (e.g., program loading) or code selection (e.g., program creation)398/9, DIAGNOSTIC TESTING398/182, TRANSMITTER375/371, Phase displacement, slip or jitter correction375/219, TRANSCEIVERS702/120Including input/output or test mode selection meansExaminersPrimary: Milord, MarceauAttorney, Agent or FirmInternational ClassH04B 17/00AbstractAn automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20) is able to test the parameters of receiver jitter tolerance and receiver sensitivity in a loopback connection arrangement, in which serial output terminals (SERTX) of the integrated circuit (10) are connected to serial input terminals (SERRX) of the integrated circuit (10). An attenuator (26), which in the disclosed embodiment includes programmable attenuators (30P, 30N) and a fixed attenuator (32), one of which is selected, is disposed in the loopback path. A deterministic jitter injector (28) is also in the loopback path, and may be implemented by way of variable length trace blocks (35P, 35N) on the test board (30). In this way, the serial output signals generated by the integrated circuit (10) are modified by the attenuator (26) and deterministic jitter injector (28) so that the signal as received at the serial input terminals (SERRX) can be at the specification limits of the circuit (10).Other References
Field of SearchHaving measuring, testing, or monitoring of system or partUsing a test signal TESTING Phase error or phase jitter Loopback mode Digital logic testing Loop-back Including test pattern generator TRANSMITTER DIAGNOSTIC TESTING Signal quality (e.g., timing jitter, distortion, signal-to-noise ratio) Including program initialization (e.g., program loading) or code selection (e.g., program creation) | |
