U.S. patents available from 1976 to present.
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Method and apparatus for calculating the remainder of a modulo division

Patent 7197526 Issued on March 27, 2007. Estimated Expiration Date: Icon_subject May 28, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Data processor having carry apparatus supporting a decimal divide operation
Patent #: 4384341
Issued on: 05/17/1983
Inventor: Tague ,   et al.

Method for generating a public key
Patent #: 5199070
Issued on: 03/30/1993
Inventor: Matsuzaki, et al.

Computer-implemented method and computer for performing modular reduction
Patent #: 5724279
Issued on: 03/03/1998
Inventor: Benaloh, et al.

Dividing method
Patent #: 6125380
Issued on: 09/26/2000
Inventor: Chung

Scheme for carrying out modular calculations based on redundant binary calculation
Patent #: 6175850
Issued on: 01/16/2001
Inventor: Ishii, et al.

Optical device for processing an optical digital signal Patent #: 6275311
Issued on: 08/14/2001
Inventor: Boffi, et al.

Inventor

Assignee

Application

No. 09321611 filed on 05/28/1999

US Classes:

708/491, Residue number714/808, Modulo-n residue check character714/784, Reed-Solomon code708/652, Coded decimal380/30, Public key708/650, Division359/107OPTICAL COMPUTING WITHOUT DIFFRACTION

Examiners

Primary: Decady, Albert
Assistant: Lamarre, Guy

International Class

G06F 7/38

Abstract

A non-iterative technique for calculating the remainder of modulo division, which requires significantly fewer operations than the traditional iterative technique for the same calculation. The number of calculations required in the present invention is independent of the number of bits of the divisor in the modulo operation. Two requirements of the non-iterative technique are that the value of the divisor D should be equal to 2n−1 (where n is the number of bits of the divisor D) and the value of the dividend N should be less than or equal to (D−1)2, but greater than or equal to zero. If these two conditions are met, the remainder R of N mod D is determined by summing the upper n 2

and lower n 2

bits of the dividend N.

Other References

  • Orton et al. (New fault tolerant techniques for residue number systems; IEEE, pp. 1453-1464; Nov. 1992).
  • Stout (Basic Electrical Measurements; 2d Ed., 1960; pp. 82-85.)
  • Burgess (Efficient RNS to binary conversion using high-radix SRT division; IEEE; pp. 1240-1243 ; 1-4 Nov. 1998).
  • Gala et al. (A high speed VLSI algorithm for A*B modulo N; IEEE, pp. 389-392 vol. 1; Aug. 12-14, 1990).
  • Bini et al. (Improved parallel polynomial division and its extensions; IEEE, pp. 131-136; Oct. 24-27, 1992.
  • Saha, A et al. (Design and FPGA implementation of efficient integer arithmetic algorithms; IEEE, pp. 4 p; Apr. 4-7, 1993).
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