Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength
Patent 7177176 Issued on February 13, 2007. Estimated Expiration Date: 
June 30, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 30, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIntegrated circuit low leakage power circuitry for use with an advanced CMOS process Patent #: 6166985 InventorsAssigneeApplicationNo. 10883609 filed on 06/30/2004US Classes:365/154, Flip-flop (electrical)365/189.05, Having particular data buffer or latch365/189.09, Including reference or bias voltage generator365/189.11, Including level shift or pull-up circuit709/250, NETWORK-TO-COMPUTER INTERFACING709/203, Client/server714/2Fault recoveryExaminersPrimary: Zarabian, AmirAssistant: Pham, Ly Duy Attorney, Agent or FirmInternational ClassesG11C 11/00G11C 5/14 G11C 7/10 AbstractIn embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).Field of SearchFlip-flop (electrical) | |
