Capacitively-coupled level restore circuits for low voltage swing logic circuits

Patent 7176719 Issued on February 13, 2007. Estimated Expiration Date:

August 31, 2024. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Speed enhancement technique for CMOS circuits
Patent #: 4985643
Issued on: 01/15/1991
Inventor: Proebsting

5237533

Semiconductor memory device having internal voltage booster circuit coupled to bit line charging/equalizing circuit
Patent #: 5828611
Issued on: 10/27/1998
Inventor: Kaneko, et al.

Median filter with embedded analog to digital converter
Patent #: 5995163
Issued on: 11/30/1999
Inventor: Fossum

6150851

Programmable analog arithmetic circuit for imaging sensor Patent #: 6166367
Issued on: 12/26/2000
Inventor: Cho

Inventor

Forbes, Leonard

Application

No. 10931379 filed on 08/31/2004

US Classes:

326/68, Field-effect transistor (e.g., JFET, MOSFET, etc.)326/83, Field-effect transistor327/96, With differential amplifier348/241, Including noise or undesired signal reduction326/30Bus or line termination (e.g., clamping, impedance matching, etc.)

Examiners

Primary: Cho, James H.

Attorney, Agent or Firm

Schwegman, Lundberg, Woessner & Kluth, P.A.

International Class

H03K 19/094

Abstract

A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a capacitively-coupled positive feedback between the differential sides. The level restore circuit further includes a reset network for resetting input and output nodes of one differential side to a first reset voltage and for resetting input and output nodes of the other differential side to a second reset voltage independent from the first reset voltage. The capacitive network reduces the effect of transistor mismatches and offsets in the level restore circuit. The level restore circuit is useful to generate output signals with a full logic levels based on input signals with a relatively low signal swing.

Other References

Bernstein, Kerry , “High-Speed Design Styles Leverage IBM Technology Prowess”, Micro News (IBM MIcroelectronics), Vol. 3, No. 4, (Aug. 1999).
Cheng, K. , et al., “A 1.2V CMOS Multiplier Using Low-Power Current-Sensing Complementary Pass-Transistor Logic”, Proc. Third Int. Conf. on Electrics, Circuits and Systems, (1996), pp. 1037-1040, no month.
Deleganes, Daniel J., et al., “Low-Voltage-Swing Logic Circuits for a 7GHz×86 Integer Core”, 2004 IEEE International Solid-State Circuits Conference, (2004), 10 pages, no month.
Fuse, Tsuneaki , et al., “A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic”, 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287 (Feb. 1997).
Glasser, Lance A., et al., The Design and Analysis of VLSI Circuits, Addison-Wesley Publishing Company, (1985), 16-21, no month.
Kayed, Somia I., et al., “CMOS Differential Pass-Transistor Logic (CMOS DPTL) Predischarge Buffer Design”, Proceedings of the Thirteenth National Radio Science Conference, Cairo, Egypt, 527-235 (Mar. 1996).
Oklobdzija, V. G., “Differential and pass-transistor CMOS logic for high performance systems”, Microelectronics Journal, 29, (1998), 679-688, no month.
Rabaey, Jan M., Digital Integrated Circuits: A Design Perspective, Section 4.2.3, Prentice Hall, Upper Saddle River, NJ, (1996), 210-222, no month.
Thompson, S. , et al., “A 90 nm technology featuring 50nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 um2 SRAM cell”, International Electron Devices Meeting, 2002. IEDM '02. Digest., (Dec. 2002), 61-64.
Tretz, C. , et al., “Performance Comparison of Differential Static CMOS Circuit Topologies in SOI Technology”, Proceedings 1998 IEEE International SOI Conference, 123-124 (Oct. 1998).
Yamashita, S. , et al., “Pass-Transistor/CMOS Collaborated Logic: The Best of Both Worlds”, 1997 Symposium on VLSI Circuits Digest of Technical Papers, (1997), 31-32, no month.
Yano, K. , et al., “Top-Down Pass-Transistor Logic Design”, IEEE Journal of Solid-State Circuits, 31(6), 792-803, (Jun. 1996).
Zimmermann, Reto , “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, 32(7), (Jul. 1997), 1079-1090.