Conflict free parallel read access to a bank interleaved branch predictor in a processor
December 19, 2020. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesExtended address generating apparatus and method Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory Method and apparatus for executing and dispatching store operations in a computer system Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock Paged memory architecture for a single chip multi-processor with physical memory pages that are swapped without latency Pipelined instruction cache and branch prediction mechanism therefor Patent #: 6101577 InventorsAssigneeApplicationNo. 09740419 filed on 12/19/2000US Classes:712/239, Branch prediction712/240, History table711/2, Addressing extended or expanded memory711/109, Shift register memory712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION711/125, Instruction data cache712/238, Branch target buffer710/53Alternately filling or emptying buffersExaminersPrimary: Pan, Daniel H.International ClassesG06F 9/42G06F 9/44 AbstractA computer system has a processor that has a prediction array that avoids conflicts when the prediction array is accessed twice in once clock cycle to retrieve predictions for two separate conditional branch instructions. The prediction array is included as part of a branch prediction logic circuit that includes a bank control logic coupled to the prediction array. The bank control logic assures the conflict noted above is avoided. The prediction array preferably comprises multiple (e.g., 4) single-ported bank memory elements, each bank comprising multiple predictions. The bank control logic uses information associated with a previously fetched and branch predicted conditional branch instruction to generate a bank number for a current branch instruction. The generated bank number corresponds to one of the banks in the prediction array. The processor preferably fetches two (or more) groups (also called “slots”) of instructions each cycle. Each slot may include one or more branch instructions that need to be branch predicted. Thus, the branch prediction logic circuit first generates a bank number for one of the slots and then generates a bank number for the other slot and uses the bank numbers to retrieve predictions from the multi-bank, single ported prediction array. The bank control logic computes the bank numbers in a manner that assures that no two consecutively generated bank numbers are identical.Other References
Field of SearchMultiple cachesHashing Incrementing, decrementing, or shifting circuitry Generating prefetch, look-ahead, jump, or predictive address Address multiplexing or address bus manipulation Including plural logical address spaces, pages, segments, blocks Predicting, look-ahead Shared memory partitioning Shared cache Memory partitioning Resolving conflict, coherency, or synonym problem Branch prediction History table Evaluation of multiple conditions or multiway branching Simultaneous parallel fetching or executing of both branch and fall-through path | |
