Clock recovery circuit with second order digital filter
Patent 7127017 Issued on October 24, 2006. Estimated Expiration Date: July 19, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
375/355, Synchronizing the sampling time of digital data375/376, Phase locked loop375/373, Phase locking341/143, Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation)375/324, Particular demodulator327/144, Using multiple clocks375/232, Adaptive331/25, Signal or phase comparator375/371, Phase displacement, slip or jitter correction326/41, Significant integrated structure, layout, or layout interconnections375/225, Data rate375/220Transmission interface between two stations or terminals
The present invention provides a method and mechanism for regenerating the clock signal and recovering the data of a serial bit data stream. According to an embodiment, a circuit for recovering data from a serial bit stream may include a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams. The circuit may further include a clock recovery loop filter having a second order filter coupled with the deserializer. The clock recovery loop filter may be configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and for generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location. The circuit may also include a phase interpolator coupled with the clock recovery loop filter and the de-serializer, configured for generating the at least one reclocking signal in accordance with the at least one control signal.
Other References
Alexander, J D. H., “Clock Recovery from Random Binary Signals, Electronic Letters”, Oct. 30, 1975, pp. 541-542, vol. 11, No. 22, The Institute of Electrical Engineers, U.K.
American National Standard for Information Systems, “Fibre Channel—Physical and Signaling Interface (FC-PH) Rev. 4.3”, proposed working draft, Jun. 1, 1994, USA.
Applied Micro Circuits Corporation, “Preliminary Device Specification for Fibre Channel and Gigabit Ethernet Transceivers S2053 and S2054”, Feb. 3, 1998.
Gore CuGLM™, “Copper Gigabaud Link”, Module FCN 7181, Aug. 1997.
Margarit, M. A. et al., “A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications”, IEEE Journal of Solid-State Circuits, Jun. 1999, pp. 761-777, vol. 34, No. 6.
Meggyesi, Z., “Fibre Channel Overview”, available in 1999 at http://www1.cern.ch/HSI/fcs/spec/overview.htm.
Nelson, C., “Fiber Channel Offers Speed, Interoperability”, EE Times—Communications Design, CMP Media Inc., available in 1999, http://techweb.cmp.com/eet/nick/corndesign/fibercha.html.
Partovi, H., et al., “A 62.5 Gb/s Multi-Standard SerDes IC”, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, Sep. 21-24, 2003, pp. 585-588, USA.
“SFI-4 (OC-192 Serdes-Framer Interface) OIF-PLL-02.0—Proposal for a Common Electrical Interface Between SONET Framer and Serializer/Deserializer Parts for OC-192 Interfaces”, Optical Internetworking Forum, OIF-SF14-01.0 Implementation Agreement, Sep. 26, 2000.
Shafire, H., “Gigibit Networking Technologies Converge”, Part 4, Communications Design, CMP Media, Inc., available in 1999 from http://techweb.cmp.com/ee/nick/comdesign/gigabito.html.
Unisys Corporation, “Fibre Channel White Paper”, 1996.
Vitesse Semiconductor Corporation, “Advance Product Information (Draft)”, Oct. 19, 1995, pp. 1-13, USA.
VLSI Technology, Inc., “Fibre Channel ENDEC+”, Product Bulletin, Aug. 1995, USA.
Webstart Communications, “Computer and Communication Standards and Cross References”, available in 1999 at http://www.cmpcmm.com/cc/standards.html.
July 19, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
