Techniques for utilization of asymmetric secondary processing resources

Patent 7100060 Issued on August 29, 2006. Estimated Expiration Date:

June 26, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Assignee

Intel Corporation

Application

No. 10184557 filed on 06/26/2002

US Classes:

713/320, Power conservation713/322, By clock speed control (e.g., clock on/off)713/323, Active/idle mode processing713/300, COMPUTER POWER CONTROL712/15, Reconfiguring713/340, Having power source monitoring714/10, Of processor712/34Including coprocessor

Examiners

Primary: Cao, Chun
Assistant: Connolly, Patrick

Attorney, Agent or Firm

Blakely, Sokoloff, Taylor & Zafman LLP

International Class

G06F 1/32

Abstract

A processor having asymmetric secondary processing resources. One disclosed embodiment includes a first execution resource to perform a first function and a second execution resource that also performs the second function, although the second processing resource is asymmetric to the first resource in that it has a lower throughput than the first processing resource. Switching logic switches execution from the first processing resource to the second processing resource in a reduced power consumption mode.

Other References

Hennessy John L. et al, Computer Organization and Design: The Hardware/Software Interface, 1998, Morgan Kaufmann Publishers, 2nd Ed., pp. 434-440, 449455, 510-516.
Seng John S et al., Reducing Power with Dynamic Critical Path Information, Dec. 2001, University of California.
Lim, Chee How, “High-Performance Microprocessor Design Under Thermal Constraints,” Dissertation submitted to Portland State University, Apr. 26, 2002.
Lim, Chee How; Daasch, W. Robert; Cai, George, “A Thermal-Aware Superscalar Microprocessor (Architecture-Level Tradeoff),” Integrated Circuit Design and Test Laboratory, Portland State University; Intel Corporation, Mar. 20, 2002, 18 pages.