Differential current evaluation circuit and sense amplifier circuit for evaluating a memory state of an SRAM semiconductor memory cell
May 2, 2023. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesCurrent-mirror type sense amplifier Output feedback control circuit for integrated circuit device Differential sense amplifier Integrated circuit having a sense amplifier Semiconductor storage device Memory cell sensing method and circuitry for bit line equalization Self cut-off type sense amplifier operable over a wide range of power supply voltages Latch type sense amplifier having a negative feedback device Buffer circuit, memory device, and integrated circuit for receiving digital signals Patent #: 6044036 InventorsAssigneeApplicationNo. 10429149 filed on 05/02/2003US Classes:365/207, Differential sensing365/208, Semiconductors365/230.08, Including particular address buffer or latch circuit arrangement365/205Flip-flop used for sensingExaminersPrimary: Elms, RichardAttorney, Agent or FirmForeign Patent References
International ClassesG11C 7/02G11C 7/00 AbstractA differential current evaluation circuit has a differential amplifier and a circuit for setting an input resistance of the current evaluation circuit. The circuit is connected to the outputs and the inputs of the differential amplifier and to signal lines. A sense amplifier circuit has a circuit section, in which a signal is available at an output in a temporally continuous manner even if, after the deactivation of the circuit connected upstream, a signal, in particular a signal supplied by the current evaluation circuit, is no longer present at its input. The differential current evaluation circuit and the sense amplifier circuit are disposed in a circuit configuration for reading out and evaluating a memory state of a semiconductor memory cell. The current evaluation circuit can be activated by a circuit section for automatic deactivation before a read operation and be automatically deactivated directly after the read operation has ended.Other References
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