Patent 7094680 Issued on August 22, 2006. Estimated Expiration Date: March 23, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
438/618, Contacting multiple semiconductive regions (i.e., interconnects)438/622, Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)438/643, At least one layer forms a diffusion barrier438/648, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/653, At least one layer forms a diffusion barrier438/656, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/660, Including heat treatment of conductive layer438/687, Copper of copper alloy conductor438/688, Aluminum or aluminum alloy conductor427/539, Oxygen containing atmosphere438/627, At least one layer forms a diffusion barrier216/18, Filling or coating of groove or through hole with a conductor to form an electrical interconnection361/234, Pinning427/561, Pretreatment of coating supply or source outside of primary deposition zone or off site427/457, DIRECT APPLICATION OF ELECTRICAL, MAGNETIC, WAVE, OR PARTICULATE ENERGY438/685, Refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/396, Stacked capacitor427/252, By decomposing metallic compound (e.g., pack process, etc.)438/239, Capacitor427/248.1, COATING BY VAPOR, GAS, OR SMOKE427/404, Metal coating427/255.28, Coating formed from vaporous or gaseous phase reaction mixture (e.g., chemical vapor deposition, CVD, etc.)438/382Resistor
A method of forming a tantalum nitride layer for integrated circuit fabrication is disclosed. In one embodiment, the method includes forming a tantalum nitride layer by chemisorbing a tantalum precursor and a nitrogen precursor on a substrate disposed in a process chamber. A nitrogen concentration of the tantalum nitride layer is reduced by exposing the substrate to a plasma annealing process. A metal-containing layer is then deposited on the tantalum nitride layer by a deposition process.
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