Cache memory eviction policy for combining write transactions

Patent 7089362 Issued on August 8, 2006. Estimated Expiration Date:

December 27, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method and apparatus for combining uncacheable write data into cache-line-sized write buffers
Patent #: 5561780
Issued on: 10/01/1996
Inventor: Glew, et al.

Speculative cache line write backs to avoid hotspots Patent #: 6119205
Issued on: 09/12/2000
Inventor: Wicki, et al.

Inventors

Assignee

Intel Corporation

Application

No. 10035034 filed on 12/27/2001

US Classes:

711/133, Entry replacement strategy711/135, Cache flushing711/144, Cache status data bit711/159, Entry replacement strategy711/170, Memory configuring710/107, Bus access regulation711/118, Caching711/129Partitioned cache

Examiners

Primary: Vital, Pierre M.
Assistant: Rojas, Midys

Attorney, Agent or Firm

Pedigo; Philip A.

Foreign Patent References

0 397 995 EP 11/01/1990

International Class

G06F 12/00

Abstract

Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.

Other References

Jim Handy, “The Cache Memory Book”, Copyright 1998, Academic Presee, second edition, p. 124.
Jim Handy, “The Cache Memory Book”, Copyright 1998, Academic Press, second Edition, pp. 156-158.
Peter G. Sassone, “Cache Consistency Protocol Comparison”, Mar. 2001, pp. 2 and 4.