U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Tracing multiple data access instructions

Patent 7080289 Issued on July 18, 2006. Estimated Expiration Date: Icon_subject October 10, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Data processor with multiple register blocks
Patent #: 4733346
Issued on: 03/22/1988
Inventor: Tanaka

Pipeline computer system having write order preservation
Patent #: 5222219
Issued on: 06/22/1993
Inventor: Stumpf, et al.

Method and apparatus for providing precise fault tracing in a superscalar microprocessor
Patent #: 5752013
Issued on: 05/12/1998
Inventor: Christensen, et al.

Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle
Patent #: 5881224
Issued on: 03/09/1999
Inventor: Ranson, et al.

Register bank bit lines
Patent #: 5917771
Issued on: 06/29/1999
Inventor: Hill

System and method for tracing program execution within a processor before and after a triggering event Patent #: 5996092
Issued on: 11/30/1999
Inventor: Augsburg, et al.

Inventors

Assignee

Application

No. 09973189 filed on 10/10/2001

US Classes:

714/45, Output recording (e.g., signature or trace)714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)712/227, Specialized instruction processing in support of testing, debugging, emulation717/128, Tracing712/228, Context preserving (e.g., context swapping, checkpointing, register windowing710/105, Protocol714/47, Performance monitoring for fault avoidance365/230.03, Plural blocks or banks714/38, Of computer software717/127, Monitoring program execution711/173Memory partitioning

Examiners

Primary: Beausoliel, Robert
Assistant: Guyton, Philip

Attorney, Agent or Firm

International Class

G06F 11/00

Abstract

A microprocessor integrated circuit 104 is provided with a trace controller 120 that is responsive to trace initiating conditions to trigger commencement of tracing operation and generation of a trace data stream. In the case of a multi-word data transfer instruction LSM, the trace controller 120 is able to trigger tracing partway through that instruction such that a subset of the transfer specified by that instruction are included within the trace data stream. All transfers subsequent to the triggering transfer may be traced with those transfers subsequent to the triggering transfer being marked with place holder codes rather than more informative full trace data for the triggering transfer.

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$16.95more info
 
Sign InRegister
Username  
Password   
forgot password?