Patent ReferencesData processor with multiple register blocks Pipeline computer system having write order preservation Method and apparatus for providing precise fault tracing in a superscalar microprocessor Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle Register bank bit lines System and method for tracing program execution within a processor before and after a triggering event Patent #: 5996092 InventorsAssigneeApplicationNo. 09973189 filed on 10/10/2001US Classes:714/45, Output recording (e.g., signature or trace)714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)712/227, Specialized instruction processing in support of testing, debugging, emulation717/128, Tracing712/228, Context preserving (e.g., context swapping, checkpointing, register windowing710/105, Protocol714/47, Performance monitoring for fault avoidance365/230.03, Plural blocks or banks714/38, Of computer software717/127, Monitoring program execution711/173Memory partitioningExaminersPrimary: Beausoliel, RobertAssistant: Guyton, Philip Attorney, Agent or FirmInternational ClassG06F 11/00AbstractA microprocessor integrated circuit 104 is provided with a trace controller 120 that is responsive to trace initiating conditions to trigger commencement of tracing operation and generation of a trace data stream. In the case of a multi-word data transfer instruction LSM, the trace controller 120 is able to trigger tracing partway through that instruction such that a subset of the transfer specified by that instruction are included within the trace data stream. All transfers subsequent to the triggering transfer may be traced with those transfers subsequent to the triggering transfer being marked with place holder codes rather than more informative full trace data for the triggering transfer. | |