Method for reducing power consumption includes comparing variance in number of time microprocessor tried to react input in predefined period to predefined variance
Portable computer with BIOS-independent power management
Power management initialization for a computer operable under a plurality of operating systems
Power management coordinator system and interface
Integrated circuit having software controllable internal clock generator and switch connecting batteries in series or parallel for power conservation
Adjusting clock frequency and voltage supplied to a processor in a computer system
Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption
System and method for cross-platform application level power management Patent #: 6131166
ApplicationNo. 10461025 filed on 06/13/2003
US Classes:713/300, COMPUTER POWER CONTROL713/320, Power conservation719/318, EVENT HANDLING OR EVENT NOTIFICATION713/323, Active/idle mode processing713/322, By clock speed control (e.g., clock on/off)713/340, Having power source monitoring327/513, With compensation for temperature fluctuations455/574Power conservation
ExaminersPrimary: Lee, Thomas C.
Assistant: Suryawanshi, Suresh K
Attorney, Agent or Firm
International ClassesG06F 1/26
AbstractMethods and systems are provided for dynamically managing power consumption in a digital system. These methods and systems broadly provide for permitting clients executing on a digital system to register for notification of power event and to request that power events occur. Registered clients are notified when a power event is requested and the requested power event is caused to occur. Power events are selected from a group comprising setpoint change, enter deep sleep mode, enter snooze mode, and change to power supply status. There may also be user-defined custom power events. If the requested power event is a setpoint change, a check is made to verify that each of the registered clients can operate at the requested setpoint. The digital system may be comprised of processor with a single processing core with a single clock or a processor with multiple processing cores and multiple clocks.