Series terminated CMOS output driver with impedance calibration
Patent 7078943 Issued on July 18, 2006. Estimated Expiration Date: 
January 28, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
January 28, 2025. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOutput buffer having distributed stages to reduce switching noise Precharging output driver circuit Wave shaping transmit circuit Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance Patent #: 6133749 InventorsApplicationNo. 11044177 filed on 01/28/2005US Classes:327/108, Current driver327/112, Push-pull326/30, Bus or line termination (e.g., clamping, impedance matching, etc.)326/86, Bus driving326/87, Having plural output pull-up or pull-down transistors326/27, With field effect-transistor326/28, With clocking326/83, Field-effect transistor330/253, Having field effect transistor710/100INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)ExaminersPrimary: Lam, Tuan T.Attorney, Agent or FirmForeign Patent References
International ClassesH03B 1/00H03K 3/00 AbstractA differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop. A first output switch is driven by a corresponding positive control signal and connected between a supply voltage and the sources of the first and second PMOS transistors. A second output switch driven by a corresponding negative control signal and connected between a ground and the sources of the first and second PMOS transistors.Other References
Field of SearchCurrent driverHaving inductive load (e.g., coil, etc.) Push-pull With field effect-transistor Bus or line termination (e.g., clamping, impedance matching, etc.) Current driving (e.g., fan in/out, off chip driving, etc.) Field-effect transistor Bus driving Having plural output pull-up or pull-down transistors Bipolar transistor Bus driving Having plural output pull-up or pull-down transistors | |
