Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
Patent 7075829 Issued on July 11, 2006. Estimated Expiration Date: August 30, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
365/185.28, Tunnel programming365/185.05, Particular connection365/185.26, Floating electrode (e.g., source, control gate, drain)257/17, With particular barrier dimension257/135, Vertical (i.e., where the source is located above the drain or vice versa)257/302, Vertical transistor438/156, Vertical channel438/157, Plural gate electrodes (e.g., dual gate, etc.)438/175, Buried channel438/176, Plural gate electrodes (e.g., dual gate, etc.)438/206, Vertical channel insulated gate field effect transistor438/263, Tunneling insulator438/268, Vertical channel438/270, Gate electrode in trench or recess in semiconductor substrate438/282, Buried channel365/182, Insulated gate devices257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling257/317, With irregularities on electrode to facilitate charging or discharging of floating electrode257/38, Three or more electrode device365/205, Flip-flop used for sensing438/269, Utilizing epitaxial semiconductor layer grown through an opening in an insulating layer505/473, Vapor deposition257/295, With ferroelectric material layer365/185.12, Parallel row lines (e.g., page mode)438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)714/725, Programmable logic array (PLA) testing257/316, With additional contacted control electrode365/185.18, Particular biasing427/8, MEASURING, TESTING, OR INDICATING365/189.01, READ/WRITE CIRCUIT257/322, With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)438/10, Electrical characteristic sensed257/25, Employing resonant tunneling257/77, Diamond or silicon carbide257/315, With floating gate electrode257/192, Field effect transistor326/39, Array (e.g., PLA, PAL, PLD, etc.)438/386, Trench capacitor365/185.07, Cross-coupled cell365/230.06, Particular decoder or driver circuit365/185.01, FLOATING GATE438/261, Multiple interelectrode dielectrics or nonsilicon compound gate insulator365/145, Ferroelectric365/185.33, Flash326/41, Significant integrated structure, layout, or layout interconnections144/4.1, Timber cutting and handling365/185.08, With volatile signal storage device438/587, Forming array of gate electrodes257/310, With high dielectric constant insulator (e.g., Ta 2 O 5 )438/183, Dummy gate438/259, Including forming gate electrode in trench or recess in substrate365/185.03, Multiple values (e.g., analog)257/213, FIELD EFFECT DEVICE438/266, Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)345/166, Optical detector365/158, Magnetoresistive438/272, Totally embedded in semiconductive layers438/398, Including texturizing storage node layer438/240, Having high dielectric constant insulator (e.g., Ta2O5, etc.)438/593, Separated by insulator (i.e., floating gate)257/51, Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction)257/325, Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions)365/185.25, Line charging (e.g., precharge, discharge, refresh)257/314, Variable threshold (e.g., floating gate memory device)438/129, With electrical circuit layout438/149, On insulating substrate or layer (e.g., TFT, etc.)428/702, O-containing438/53, Having diaphragm element257/234Single strip of sensors (e.g., linear imager)
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.
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August 30, 2021. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
