Patent ReferencesRedundant bus bridge systems and methods using selectively synchronized clock signals Patent #: 5991844 InventorsAssigneeApplicationNo. 10881553 filed on 06/30/2004US Classes:710/314, Common protocol (e.g., PCI to PCI)710/300, Bus expansion or extension710/312, Multiple bridges710/316, Path selecting switch326/86, Bus driving710/260, INTERRUPT PROCESSING370/401Bridge or gateway between networksExaminersPrimary: Auve, Glenn A.Assistant: Lee, Christopher E. Attorney, Agent or FirmInternational ClassesG06F 13/36G06F 13/00 AbstractA data processing system includes first and second data processing devices coupled to each other through a midplane. Each data processing device includes a data storage processor; a root complex coupled to the data storage processor; and a switch device coupled between the root complex and at least one end point device. The switch device includes a first transparent bridge coupled to the root complex and a second transparent bridge coupled between the first transparent bridge and the at least one end point device, a first data path connected between the first transparent bridge and the midplane and a second data path connected between the first transparent bridge and the midplane through a non-transparent bridge. The first data path of the first data processing device is connected to the second data path of the second data processing device through the midplane and the second data path of the first data processing device is connected to the first data path of the second data processing device through the midplane, such that data transmitted between the root complexes of each of the first and second data processing devices is transmitted through only one non-transparent bridge. | |