U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method of manufacturing a semiconductor device

Patent 7052943 Issued on May 30, 2006. Estimated Expiration Date: Icon_subject March 15, 2022. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3535775

Method of providing gettering sites through electrode windows
Patent #: 4371403
Issued on: 02/01/1983
Inventor: Ikubo ,   et al.

Heteroepitaxy of multiconstituent material by means of a _template layer
Patent #: 4477308
Issued on: 10/16/1984
Inventor: Gibson ,   et al.

Method for manufacturing crystalline film
Patent #: 4534820
Issued on: 08/13/1985
Inventor: Mori ,   et al.

Method of making a thin film transistor with laser recrystallized source and drain
Patent #: 4727044
Issued on: 02/23/1988
Inventor: Yamazaki

Method to getter contamination in semiconductor devices
Patent #: 5244819
Issued on: 09/14/1993
Inventor: Yue

Thin film silicon semiconductor device and process for producing thereof
Patent #: 5248630
Issued on: 09/28/1993
Inventor: Serikawa, et al.

Single-alignment-level lithographic technique for achieving self-aligned features
Patent #: 5275896
Issued on: 01/04/1994
Inventor: Garofalo, et al.

Method for manufacturing semiconductor device
Patent #: 5403772
Issued on: 04/04/1995
Inventor: Zhang, et al.

Method of fabricating a semiconductor device
Patent #: 5426064
Issued on: 06/20/1995
Inventor: Zhang, et al.

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Inventors

Assignee

Application

No. 10097641 filed on 03/15/2002

US Classes:

438/166, Including recrystallization step438/476, By layers which are coated, contacted, or diffused438/150, Specified crystallographic orientation438/164, Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.)438/770Oxidation

Examiners

Primary: Booth, Richard A.

Attorney, Agent or Firm

Foreign Patent References

  • 0 651 431 EP 05/01/1995
  • 05-109737 JP 04/01/1993
  • 06-151414 JP 05/01/1994
  • 07-130652 JP 05/01/1995
  • 07-183540 JP 07/01/1995
  • 08-78329 JP 03/01/1996
  • 09-074207 JP 03/01/1997
  • 10-055951 JP 02/01/1998
  • 3032801 JP 09/01/1998
  • 2000-105081 JP 04/01/2000
  • 2000-260777 JP 09/01/2000
  • 2001-210828 JP 08/01/2001
  • 2001-267264 JP 09/01/2001

International Class

H01L 21/84

Abstract

A technique of using a metal element that has a catalytic action over crystallization of a semiconductor film to obtain a crystalline semiconductor film and then effectively removing the metal element remaining in the film is provided. A first semiconductor film (104) having a crystal structure is formed on a substrate. A barrier layer (105) and a second semiconductor film (106) containing a rare gas element are formed on the first semiconductor film (104). A metal element contained in the first semiconductor film (104) is moved to the second semiconductor film (106) through the barrier layer (105) by heat treatment for gettering.

Other References

  • U.S. Appl. No. 10/056,055, including specification, drawings and filing receipt, “Semiconductor Device and Manufacturing Method of the Same”, Osamu Nakamura et al., filed Jan. 28, 2002.
  • U.S. Appl. No. 10/072,931, including specification, drawings and filing receipt, “Method of Manufacturing a Semiconductor Device”, Shunpei Yamazaki et al., filed Feb. 12, 2002.
  • U.S. Appl. No. 10/074,050, including specification, drawings and filing receipt, “Method of Manufacturing a Semiconductor Device”, Shunpei Yamazaki et al., filed Feb. 14, 2002.
  • U.S. Appl. No. 10/051,064, including specification, drawings and filing receipt, “Semiconductor Device and Method of Manufacturing the Same”, filed Jan. 18, 2002.
  • U.S. Appl. No. 10/066,542, including specification, drawings and filing receipt, “Semiconductor Device and Method for Manufacturing the Same”, filed Feb. 5, 2002.
  • U.S. Appl. No. 10/020,961, including specification, drawings and filing receipt, “Method of Manufacturing Semiconductor Device and Semiconductor Device”, filed Dec. 19, 2001.
  • M. Miyake et al., “Characteristics of Buried-Channel pMOS Devices with Shallow Counter-Doped Layers Fabricated Using Channel Preamorphization”, IEEE Transactions on Electron Devices, vol. 43, No. 3, Mar. 1996, pp. 444-449.
  • L. S. Lee et al., “Argon Ion-Implantation on Polysilicon or Amorphous-Silicon for Boron Penetration Suppression in p+ pMOSFET”, IEEE Transactions on Electron Devices, vol. 45, No. 8, Aug. 1998, pp. 1737-1744.
  • D.J. Llewellyn et al., Implantation and Annealing of Cu in InP for Electrical Isolation: Microstructural Characterisation, IEEE, 1997, pp. 313-316.
  • Kevin S. Jones et al., Boron Diffusion Upon Annealing of Laser Thermal Processed Silicon, IEEE, 2000, pp. 111-114.
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