System and method for using multiple working memories to improve microprocessor security

Patent 7036002 Issued on April 25, 2006. Estimated Expiration Date:

June 25, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Operating system for a multi-tasking operating environment
Patent #: 5012409
Issued on: 04/30/1991
Inventor: Fletcher, et al.

Data processor
Patent #: 5029069
Issued on: 07/02/1991
Inventor: Sakamura

Method and apparatus for the context switching of devices
Patent #: 5127098
Issued on: 06/30/1992
Inventor: Rosenthal, et al.

Determination of time of execution of predetermined data processing routing in relation to occurrence of prior externally observable event
Patent #: 5249294
Issued on: 09/28/1993
Inventor: Griffin, III, et al.

Interrupt test circuit for microprocessor system
Patent #: 5280618
Issued on: 01/18/1994
Inventor: Takagi

Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
Patent #: 5357617
Issued on: 10/18/1994
Inventor: Davis, et al.

Method and apparatus for rapidly switching processes in a computer system
Patent #: 5361337
Issued on: 11/01/1994
Inventor: Okin

System and method for custom context switching
Patent #: 5613114
Issued on: 03/18/1997
Inventor: Anderson, et al.

Preemptive multithreading computer system with clock activated interrupt Patent #: 5694604
Issued on: 12/02/1997
Inventor: Reiffin

Inventor

Ugon, Michel

Application

No. 09242974 filed on 06/25/1998

US Classes:

712/228, Context preserving (e.g., context swapping, checkpointing, register windowing712/234, Conditional branching711/202, Address mapping (e.g., conversion, translation)710/260, INTERRUPT PROCESSING712/245, Processing sequence control (i.e., microsequencing)718/108Context switching

Examiners

Primary: Chan, Eddie P.
Assistant: Li, Aimee J.

Attorney, Agent or Firm

International Class

G06F 7/38

Abstract

An unpredictable microprocessor or microcomputer comprises a processor (1), a first working memory (51), a main memory (6) containing an operating system, a main program (P1) and a secondary program (P2), a second working memory (52), and switching means which, during the performance of the programs, makes it possible to switch from using one of the two working memories (51, 52) to using the other working memory, while preserving their contents. Switching means comprise at least one first block of registers (54) for storing the operating context of the programs in the main memory and a switching circuit (53) for enabling one of the working memories and the access registers (A1–a3) (d1–d3) associated with each memory (51, 52, 6) and controlled by said switching circuit (53).

Other References

InstantWeb. “On-line Computing Dictionary”. http://www.instantweb.com/foldoc/foldoc.cgi?computer+dictionary Search terms: Random Access Memory; Buffer; Random.